Searched refs:MaskLo (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1748 SDValue MaskLo, MaskHi; in SplitVecRes_MLOAD() local
1750 SplitVecRes_SETCC(Mask.getNode(), MaskLo, MaskHi); in SplitVecRes_MLOAD()
1753 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecRes_MLOAD()
1833 SDValue MaskLo, MaskHi; in SplitVecRes_MGATHER() local
1838 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecRes_MGATHER()
2524 SDValue MaskLo, MaskHi; in SplitVecOp_MGATHER() local
2527 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecOp_MGATHER()
2595 SDValue MaskLo, MaskHi; in SplitVecOp_MSTORE() local
2600 GetSplitVector(Mask, MaskLo, MaskHi); in SplitVecOp_MSTORE()
2681 SDValue MaskLo, MaskHi; in SplitVecOp_MSCATTER() local
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| H A D | TargetLowering.cpp | 1852 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
1857 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) in SimplifyDemandedBits()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2591 Register MaskLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2594 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo) in selectG_PTRMASK()
2598 .addReg(MaskLo); in selectG_PTRMASK()
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| H A D | AMDGPURegisterBankInfo.cpp | 2643 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0); in applyMappingImpl() local
2644 MRI.setRegBank(MaskLo, *BankLo); in applyMappingImpl()
2652 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23402 static const int MaskLo[] = { 0, 0, 2, 2 }; in LowerVSETCC() local
23404 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()
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