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Searched refs:Mask1 (Results 1 – 11 of 11) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp297 int Mask0, Mask1; in convertLogicOp() local
300 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
306 Mask = Mask0 & Mask1; in convertLogicOp()
309 Mask = Mask0 | Mask1; in convertLogicOp()
312 Mask = Mask0 ^ Mask1; in convertLogicOp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp209 VPValue *Mask1 = getPredicatedMask(Region1); in mergeReplicateRegions() local
211 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegions()
218 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegions()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp861 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
863 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
865 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
868 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSystemRegister.td45 // Mask1 Mask2 Mask3 Enc12, Name
H A DARMISelLowering.cpp5942 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
5944 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1631 uint64_t Mask1 = computeKnownBits(Mask, 0, II).One.getZExtValue(); in visitCallInst() local
1633 uint64_t C = Bytes1 & Mask1; in visitCallInst()
H A DInstCombineCompares.cpp3179 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3185 Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6213 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
6214 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
6217 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
20604 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
20615 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
20623 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
20631 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6038 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
6039 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp7586 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
7588 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
7594 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
7596 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
43847 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
43853 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
43854 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
43901 SmallVector<int> Mask0, Mask1; in combineHorizOpWithShuffle() local
43905 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
43912 scaleShuffleElements(Mask1, 2, ScaledMask1)) { in combineHorizOpWithShuffle()
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp15125 Value *Mask1 = Builder.CreateCall(Lvs, Ops[0], "mask1"); in EmitPPCBuiltinExpr() local
15130 Ops.push_back(Mask1); in EmitPPCBuiltinExpr()