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Searched refs:MTC0 (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/sys/mips/include/
H A Dasm.h502 #define MTC0 mtc0 macro
507 #define MTC0 dmtc0 macro
/freebsd-13.1/sys/mips/mips/
H A Dexception.S331 MTC0 v0, MIPS_COP_0_EXC_PC ;\
528 MTC0 a0, MIPS_COP_0_EXC_PC # set return address
630 MTC0 k1, MIPS_COP_0_EXC_PC
815 MTC0 t2, MIPS_COP_0_EXC_PC # set return address
1232 MTC0 k0, MIPS_COP_0_ERROR_PC # set return address
H A Dswtch.S101 MTC0 a0, MIPS_COP_0_EXC_PC # set return address
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp682 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
H A DMipsScheduleP5600.td93 MFC0, MTC0)>;
H A DMipsScheduleGeneric.td450 def : InstRW<[GenericWriteCOP0], (instrs MTC0)>;
H A DMipsInstrInfo.td2426 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>,
2821 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp5803 case Mips::MTC0: in checkTargetMatchPredicate()