| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1161 MSTORE, enumerator
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| H A D | SelectionDAGNodes.h | 1356 case ISD::MSTORE:
1393 case ISD::MSTORE:
2359 N->getOpcode() == ISD::MSTORE;
2400 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2422 return N->getOpcode() == ISD::MSTORE;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 115 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
170 setOperationAction(ISD::MSTORE, T, Custom); in initializeHVXLowering()
218 setOperationAction(ISD::MSTORE, BoolW, Custom); in initializeHVXLowering()
1711 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1843 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
1866 if (MemOpc == ISD::MSTORE) { in SplitHvxMemOp()
2069 case ISD::MSTORE: in LowerHvxOperation()
2122 case ISD::MSTORE: return LowerHvxMaskedOp(Op, DAG); in LowerHvxOperation()
2174 case ISD::MSTORE: in LowerHvxOperationWrapper()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 390 case ISD::MSTORE: return "masked_store"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 2172 case ISD::MSTORE: in SplitVectorOperand()
4542 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break; in WidenVectorOperand()
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| H A D | SelectionDAG.cpp | 693 case ISD::MSTORE: { in AddNodeIDCustom()
7681 AddNodeIDNode(ID, ISD::MSTORE, VTs, Ops); in getMaskedStore()
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| H A D | LegalizeDAG.cpp | 1163 case ISD::MSTORE: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 1512 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N), in PromoteIntegerOperand()
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| H A D | DAGCombiner.cpp | 1723 case ISD::MSTORE: return visitMSTORE(N); in visit()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 550 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
614 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
724 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
798 setOperationAction(ISD::MSTORE, VT, Custom); in RISCVTargetLowering()
2542 case ISD::MSTORE: in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 650 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1235 setOperationAction(ISD::MSTORE, VT, Custom); in AArch64TargetLowering()
1556 setOperationAction(ISD::MSTORE, VT, Custom); in addTypeForFixedLengthSVE()
4899 case ISD::MSTORE: in LowerOperation()
15232 assert((N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::MSTORE) && in foldTruncStoreOfExt()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1453 case ISD::MSTORE: in SelectT2AddrModeImm7Offset()
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| H A D | ARMISelLowering.cpp | 264 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
331 setOperationAction(ISD::MSTORE, VT, Legal); in addMVEVectorTypes()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1407 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1587 setOperationAction(ISD::MSTORE, VT, Custom); in X86TargetLowering()
1741 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1748 setOperationAction(ISD::MSTORE, VT, Legal); in X86TargetLowering()
1893 setOperationAction(ISD::MSTORE, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2035 setTargetDAGCombine(ISD::MSTORE); in X86TargetLowering()
30569 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG); in LowerOperation()
51211 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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