| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 1392 case ISD::MLOAD:
2339 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2342 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2358 return N->getOpcode() == ISD::MLOAD ||
2371 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2386 return N->getOpcode() == ISD::MLOAD;
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| H A D | ISDOpcodes.h | 1160 MLOAD, enumerator
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 114 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
169 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
217 setOperationAction(ISD::MLOAD, BoolW, Custom); in initializeHVXLowering()
1711 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1713 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
1843 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
1850 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
2068 case ISD::MLOAD: in LowerHvxOperation()
2121 case ISD::MLOAD: in LowerHvxOperation()
2166 case ISD::MLOAD: in LowerHvxOperationWrapper()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 389 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 939 case ISD::MLOAD: in SplitVectorResult()
3004 case ISD::MLOAD: in WidenVectorResult()
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| H A D | LegalizeIntegerTypes.cpp | 73 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1514 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| H A D | SelectionDAG.cpp | 686 case ISD::MLOAD: { in AddNodeIDCustom()
7634 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| H A D | DAGCombiner.cpp | 1721 case ISD::MLOAD: return visitMLOAD(N); in visit()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 549 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
613 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
723 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
797 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
2540 case ISD::MLOAD: in LowerOperation()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1450 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
3992 case ISD::MLOAD: in Select()
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| H A D | ARMISelLowering.cpp | 263 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
330 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
10204 case ISD::MLOAD: in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 652 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1164 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1234 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1265 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1302 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1554 setOperationAction(ISD::MLOAD, VT, Custom); in addTypeForFixedLengthSVE()
4944 case ISD::MLOAD: in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1406 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
1586 setOperationAction(ISD::MLOAD, VT, Custom); in X86TargetLowering()
1740 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1747 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1892 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2033 setTargetDAGCombine(ISD::MLOAD); in X86TargetLowering()
30568 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
51209 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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