Home
last modified time | relevance | path

Searched refs:MCInstrDesc (Results 1 – 25 of 184) sorted by relevance

12345678

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h37 class MCInstrDesc; variable
329 const MCInstrDesc &MCID) { in BuildMI()
392 const MCInstrDesc &MCID) { in BuildMI()
402 const MCInstrDesc &MCID) { in BuildMI()
411 const MCInstrDesc &MCID) { in BuildMI()
421 const MCInstrDesc &MCID) { in BuildMI()
428 const MCInstrDesc &MCID) { in BuildMI()
445 const MCInstrDesc &MCID, bool IsIndirect,
452 const MCInstrDesc &MCID, bool IsIndirect,
459 const MCInstrDesc &MCID, bool IsIndirect,
[all …]
H A DDFAPacketizer.h45 class MCInstrDesc; variable
79 bool canReserveResources(const MCInstrDesc *MID);
83 void reserveResources(const MCInstrDesc *MID);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h25 class MCInstrDesc; variable
54 const MCInstrDesc &II,
69 const MCInstrDesc *II,
80 const MCInstrDesc *II,
113 const MCInstrDesc &DbgValDesc,
H A DInstrEmitter.cpp193 const MCInstrDesc &II, in CreateVirtualRegisters()
301 const MCInstrDesc *II, in AddRegisterOperand()
310 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
372 const MCInstrDesc *II, in AddOperand()
633 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
716 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
770 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF); in EmitDbgInstrRef()
877 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValueFromSingleOp()
902 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL); in EmitDbgLabel()
941 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrInfo.h32 const MCInstrDesc *Desc; // Raw array to allow static init'n
47 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
62 const MCInstrDesc &get(unsigned Opcode) const { in get()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
H A DPPCExpandAtomicPseudoInsts.cpp55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
113 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
114 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
212 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
213 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
H A DPPCFrameLowering.cpp656 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
658 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
666 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 in emitPrologue()
668 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
677 const MCInstrDesc &HashST = in emitPrologue()
1575 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
1577 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
1581 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitEpilogue()
1583 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
1587 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 in emitEpilogue()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp21 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
33 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
42 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kMCCodeEmitter.cpp54 const MCInstrDesc &Desc, uint64_t &Buffer,
59 const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
64 const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
77 const MCInstrDesc &Desc, in encodeBits()
108 const MCInst &MI, const MCInstrDesc &Desc, in encodeReg()
183 const MCInst &MI, const MCInstrDesc &Desc, in encodeImm()
319 const MCInstrDesc &Desc = MCII.get(Opcode); in encodeInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp57 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
66 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
76 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
83 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
H A DScoreboardHazardRecognizer.cpp123 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
178 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
161 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
219 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
275 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
276 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
354 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
420 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
513 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
H A DM68kInstrInfo.h312 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
315 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
322 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h423 const MCInstrDesc &DefMCID,
427 const MCInstrDesc &DefMCID,
431 const MCInstrDesc &UseMCID,
435 const MCInstrDesc &UseMCID,
439 const MCInstrDesc &DefMCID,
441 const MCInstrDesc &UseMCID,
446 const MCInstrDesc &DefMCID, unsigned DefAdj,
449 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
877 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
H A DMLxExpansionPass.cpp184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
H A DARMHazardRecognizer.cpp29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
53 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h24 class MCInstrDesc; variable
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
312 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
323 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
337 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
464 MCInstrDesc const &Desc = in checkNewValues()
539 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h765 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
768 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
771 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
780 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
825 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) { in getOperandSize()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp308 const MCInstrDesc &Desc = MCII.get(Opcode); in encodeInstruction()
420 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getSDWASrcEncoding()
521 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
536 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp127 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
194 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
357 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
416 const MCInstrDesc &MID = UseMI->getDesc(); in updateAddUses()
444 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
626 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
673 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h29 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp247 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, in computeMaxLatency()
262 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) { in verifyOperands()
293 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateWrites()
462 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateReads()
545 const MCInstrDesc &MCDesc = MCII.get(Opcode); in createInstrDescImpl()

12345678