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Searched refs:MCII (Results 1 – 25 of 90) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h45 MCInstrInfo const &MCII; variable
52 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
171 unsigned getCVIResources(MCInstrInfo const &MCII,
178 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
180 bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
214 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
222 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
228 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
243 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
245 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
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H A DHexagonMCInstrInfo.cpp41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
159 HexagonMCShuffle(Context, true, MCII, STI, MCB); in canonicalizePacketImpl()
230 if (isConstExtended(MCII, MCI)) in extendIfNeeded()
231 addConstExtender(Context, MCII, MCB, MCI); in extendIfNeeded()
250 return MCII.get(MCI.getOpcode()); in getDesc()
369 return MCII.getName(MCI.getOpcode()); in getName()
631 const uint64_t V = getType(MCII, MCI); in isHVX()
927 if (!isPredicated(MCII, MCI)) in predicateInfo()
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H A DHexagonMCChecker.cpp56 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
74 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
187 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in init()
200 : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI), in HexagonMCChecker()
208 : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII), in HexagonMCChecker()
290 if (HexagonMCInstrInfo::isSoloAX(MCII, I)) { in checkAXOK()
343 if (HexagonMCInstrInfo::isCofMax1(MCII, I)) { in checkCOFMax1()
375 if (HexagonMCInstrInfo::isDuplex(MCII, MCI)) in checkSlots()
422 if (!HexagonMCInstrInfo::isNewValue(MCII, I)) in checkNewValues()
563 if (HexagonMCInstrInfo::isCVINew(MCII, I) && in checkRegisterCurDefs()
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H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
107 HexagonMCShuffler MCS(Context, Fatal, MCII, STI, MCB); in HexagonMCShuffle()
132 llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
173 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB); in HexagonMCShuffle()
182 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
193 bool bhasDuplex = HexagonMCInstrInfo::hasDuplex(MCII, MCB); in HexagonMCShuffle()
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H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
168 MCInstrInfo const &MCII, in HexagonShuffler() argument
170 : Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) { in HexagonShuffler()
182 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
371 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
404 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
448 if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, ID)) in GetPacketSummary()
453 if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { in GetPacketSummary()
460 switch (HexagonMCInstrInfo::getType(MCII, ID)) { in GetPacketSummary()
485 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
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H A DHexagonMCShuffler.h31 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
33 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
37 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
40 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
56 bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII,
58 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
466 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
623 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); in getExprOpValue()
683 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind); in getExprOpValue()
726 if (HexagonMCInstrInfo::isNewValue(MCII, MI) && in getMachineOpValue()
747 if (HexagonMCInstrInfo::isVector(MCII, Inst)) { in getMachineOpValue()
751 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst)) in getMachineOpValue()
753 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst)) in getMachineOpValue()
759 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { in getMachineOpValue()
763 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && in getMachineOpValue()
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H A DHexagonAsmBackend.cpp44 std::unique_ptr <MCInstrInfo> MCII; member in __anon42d4c60b0111::HexagonAsmBackend
66 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
542 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
543 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
549 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
552 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
675 *MCII, CrntHMI, in relaxInstruction()
676 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI)); in relaxInstruction()
744 Context, *MCII, *RF.getSubtargetInfo(), Inst, in finishLayout()
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H A DHexagonShuffler.h97 HexagonCVIResource(MCInstrInfo const &MCII,
117 HexagonInstr(MCInstrInfo const &MCII, in HexagonInstr() argument
120 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
174 MCInstrInfo const &MCII; variable
203 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
236 return (*Pred)(MCII, Inst); in HasInstWith()
H A DHexagonMCCodeEmitter.h36 MCInstrInfo const &MCII; variable
50 : MCT(MCT), MCII(MII) {} in HexagonMCCodeEmitter()
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/
H A DCustomBehaviour.h37 const MCInstrInfo &MCII; variable
40 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
41 : STI(STI), MCII(MCII) {} in InstrPostProcess()
59 const MCInstrInfo &MCII; variable
63 const MCInstrInfo &MCII) in CustomBehaviour() argument
64 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp298 const MCInstrInfo &MCII) { in createInstrPostProcess() argument
302 return std::make_unique<mca::InstrPostProcess>(STI, MCII); in createInstrPostProcess()
307 return std::make_unique<mca::InstrPostProcess>(STI, MCII); in createInstrPostProcess()
428 assert(MCII && "Unable to create instruction info!"); in main()
431 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
504 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get()); in main()
517 TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx)); in main()
536 createInstrPostProcess(TheTriple, *STI, *MCII); in main()
581 *STI, *MCII, CE, ShowEncoding, Insts, *IP)); in main()
606 createCustomBehaviour(TheTriple, *STI, S, *MCII); in main()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
202 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
205 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in __anonb84a014f0111::WebAssemblyMCCodeEmitter
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) : MCII(MCII) {} in WebAssemblyMCCodeEmitter() argument
55 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
56 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
87 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp68 const MCInstrInfo &MCII, in computeInstrLatency() argument
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
111 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon8dcf3ba80111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
191 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
460 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
471 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
491 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { in getSingleInstruction()
521 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && in getSingleInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anonfa4218590111::R600MCCodeEmitter
36 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
86 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
89 return new R600MCCodeEmitter(MCII, MRI); in createR600MCCodeEmitter()
98 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
169 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp34 const MCInstrInfo &MCII; member in __anon8d1633830111::BPFMCCodeEmitter
41 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {} in BPFMCCodeEmitter()
75 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII, in createBPFMCCodeEmitter() argument
78 return new BPFMCCodeEmitter(MCII, MRI, true); in createBPFMCCodeEmitter()
81 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, in createBPFbeMCCodeEmitter() argument
84 return new BPFMCCodeEmitter(MCII, MRI, false); in createBPFbeMCCodeEmitter()
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/lib/AMDGPU/
H A DAMDGPUCustomBehaviour.h27 AMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in AMDGPUInstrPostProcess() argument
28 : InstrPostProcess(STI, MCII) {} in AMDGPUInstrPostProcess()
39 const MCInstrInfo &MCII);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
108 const MCInstrInfo &MCII; variable
H A DAVRMCELFStreamer.h26 std::unique_ptr<MCInstrInfo> MCII; variable
34 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
42 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
47 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
77 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
81 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp43 MCInstrInfo const &MCII; member in __anon715ea9c10111::RISCVMCCodeEmitter
46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in RISCVMCCodeEmitter() argument
47 : Ctx(ctx), MCII(MCII) {} in RISCVMCCodeEmitter()
95 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, in createRISCVMCCodeEmitter() argument
98 return new RISCVMCCodeEmitter(Ctx, MCII); in createRISCVMCCodeEmitter()
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
272 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); in getImmOpValue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCCodeEmitter.cpp42 const MCInstrInfo &MCII; member in __anon39a8ba890111::VEMCCodeEmitter
47 : MCII(mcii), Ctx(ctx) {} in VEMCCodeEmitter()
161 MCCodeEmitter *llvm::createVEMCCodeEmitter(const MCInstrInfo &MCII, in createVEMCCodeEmitter() argument
164 return new VEMCCodeEmitter(MCII, Ctx); in createVEMCCodeEmitter()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp128 std::unique_ptr<const MCInstrInfo> MCII; member in __anon32cc2f430111::X86AsmBackend
147 MCII(T.createMCInstrInfo()) { in X86AsmBackend()
327 const MCInstrDesc &Desc = MCII.get(Opcode); in getCondFromBranch()
336 X86::CondCode CC = getCondFromBranch(MI, MCII); in classifySecondInstInMacroFusion()
343 const MCInstrDesc &Desc = MCII.get(Opcode); in isRIPRelative()
363 if (isRIPRelative(Inst, MCII)) in isFirstMacroFusibleInst()
382 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode()); in determinePaddingPrefix()
438 if (!isFirstMacroFusibleInst(Cmp, *MCII)) in isMacroFused()
443 classifySecondInstInMacroFusion(Jcc, *MCII); in isMacroFused()
548 if (isPrefix(PrevInst, *MCII)) in canPadInst()
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