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Searched refs:LoadedVT (Results 1 – 6 of 6) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1590 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1603 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1608 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1614 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1665 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1696 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1742 EVT LoadedVT; in tryMVEIndexedLoad() local
1754 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
1755 if (!LoadedVT.isVector()) in tryMVEIndexedLoad()
1770 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp843 EVT LoadedVT = LD->getMemoryVT(); in tryLoad() local
850 if (!LoadedVT.isSimple()) in tryLoad()
885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
894 assert(LoadedVT == MVT::v2f16 && "Unexpected vector type"); in tryLoad()
1000 EVT LoadedVT = MemSD->getMemoryVT(); in tryLoadVector() local
1002 if (!LoadedVT.isSimple()) in tryLoadVector()
1023 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp71 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoad() local
78 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in SelectIndexedLoad()
80 assert(LoadedVT.isSimple()); in SelectIndexedLoad()
81 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad()
152 assert(LoadedVT.getSizeInBits() <= 32); in SelectIndexedLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5131 EVT LoadedVT = LD->getMemoryVT(); in Select() local
5150 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5151 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5162 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5163 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5187 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5188 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5199 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5201 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7495 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
7500 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
7501 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
7503 LoadedVT.isVector()) { in expandUnalignedLoad()
7512 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
7513 if (LoadedVT != VT) in expandUnalignedLoad()
7523 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
7528 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
7579 LoadedVT); in expandUnalignedLoad()
7585 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
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H A DDAGCombiner.cpp5229 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
5231 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
5245 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()