Home
last modified time | relevance | path

Searched refs:LoadVT (Results 1 – 16 of 16) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4633 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
4639 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
4679 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
4681 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
4682 if (LoadVT.isVector()) { in adjustLoadValueType()
4712 EVT LoadVT = M->getValueType(0); in lowerIntrinsicLoad() local
4729 if (isTypeLegal(LoadVT)) { in lowerIntrinsicLoad()
6092 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) || in lowerImage()
6404 MVT LoadVT = VT.getSimpleVT(); in lowerSBuffer() local
6405 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1; in lowerSBuffer()
[all …]
H A DSIISelLowering.h238 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h546 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
551 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
554 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
2557 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
2561 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
2574 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h930 EVT LoadVT = EVT::getEVT(Src);
934 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1235 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1239 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp7568 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
7576 if (LoadVT.isVector()) in getMemCmpLoad()
7603 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
7681 MVT LoadVT; in visitMemCmpBCmpCall() local
7687 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
7690 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
7695 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
7699 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
7702 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); in visitMemCmpBCmpCall()
7703 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); in visitMemCmpBCmpCall()
[all …]
H A DLegalizeDAG.cpp882 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
884 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
888 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
890 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp7346 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
7353 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
7358 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
7368 LoadVT, SL, /*LegalTypes=*/false); in scalarizeVectorLoad()
7369 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
7371 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp5645 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
5647 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
5653 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
5658 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
17093 EVT LoadVT; in getStoreMergeCandidates() local
17097 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
17099 if (MemVT != LoadVT) in getStoreMergeCandidates()
17131 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2558 EVT LoadVT = EltVT; in LowerFormalArguments() local
2560 LoadVT = MVT::i8; in LowerFormalArguments()
2565 LoadVT = MVT::i32; in LowerFormalArguments()
2567 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments()
2581 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
2593 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1329 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp5377 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
5380 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5384 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
5388 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5389 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
40268 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
40270 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
47786 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
47787 if (SDValue VZLoad = narrowLoadToVZLoad(LN, MemVT, LoadVT, DAG)) { in combineX86INT_TO_FP()
47815 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineCVTP2I_CVTTP2I() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6406 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
6407 if (LoadVT == MVT::i16) in combineBSWAP()
6408 LoadVT = MVT::i32; in combineBSWAP()
6411 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14690 EVT LoadVT = VT; in performLDNT1Combine() local
14692 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
14695 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
14696 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
14721 EVT LoadVT = VT; in performLD1ReplicateCombine() local
14723 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
14726 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15185 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in CombineBaseUpdate() local
15186 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in CombineBaseUpdate()
17630 EVT LoadVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
17633 LoadVT = LoadVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVEExtCombine()
17649 VT, Chain, Ptr, MPI, LoadVT, Align(4)); in PerformMVEExtCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14874 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
14876 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
14877 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()