| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 424 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
442 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| H A D | X86InstrInfo.cpp | 6602 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
6604 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
6606 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
6777 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
6790 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
6800 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
6807 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear()
6822 EVT VT = Load1->getValueType(0); in shouldScheduleLoadsNear()
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| H A D | X86ISelLowering.cpp | 45783 SDValue Load1 = in combineLoad() local
45792 Load1.getValue(1), Load2.getValue(1)); in combineLoad()
45794 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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| H A D | ARMBaseInstrInfo.cpp | 1914 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1920 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1923 switch (Load1->getMachineOpcode()) { in areLoadsFromSameBasePtr()
1965 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1966 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1970 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
1974 if (isa<ConstantSDNode>(Load1->getOperand(1)) && in areLoadsFromSameBasePtr()
1976 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2011 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
2012 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1309 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, in areLoadsFromSameBasePtr() argument
1323 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, in shouldScheduleLoadsNear() argument
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 185 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
199 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
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| H A D | SIInstrInfo.cpp | 133 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr() argument
136 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr()
140 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr()
149 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
153 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
181 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); in areLoadsFromSameBasePtr()
184 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
190 dyn_cast<ConstantSDNode>(Load1->getOperand(1)); in areLoadsFromSameBasePtr()
206 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
222 SDValue Off1 = Load1->getOperand(OffIdx1); in areLoadsFromSameBasePtr()
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 1193 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8); in applyMappingLoad() local
1197 B.buildInsert(MI.getOperand(0), Ins0, Load1, 64); in applyMappingLoad()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1829 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); in SplitHvxMemOp() local
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
1833 Load0.getValue(1), Load1.getValue(1)) }, dl); in SplitHvxMemOp()
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| H A D | HexagonISelLowering.cpp | 3061 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); in LowerUnalignedLoad() local
3064 {Load1, Load0, BaseNoOff.getOperand(0)}); in LowerUnalignedLoad()
3066 Load0.getValue(1), Load1.getValue(1)); in LowerUnalignedLoad()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | DataFlowSanitizer.cpp | 2160 Value *Load1 = in loadShadowOriginSansLoadTracking() local
2162 return {combineShadows(Load, Load1, Pos), Origin}; in loadShadowOriginSansLoadTracking()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10374 LoadSDNode *Load1 = cast<LoadSDNode>(Op1); in tryToFoldExtendSelectLoad() local
10376 if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) || in tryToFoldExtendSelectLoad()
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