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Searched refs:LiveIn (Results 1 – 25 of 27) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DSourcePrinter.cpp156 ActiveCols[ColIdx].LiveIn = LV.liveAtAddress(ThisAddr); in update()
160 << ColIdx << ": LiveIn=" << ActiveCols[ColIdx].LiveIn in update()
163 if (!ActiveCols[ColIdx].LiveIn && !ActiveCols[ColIdx].LiveOut) in update()
175 bool LiveIn = LV.liveAtAddress(ThisAddr); in update() local
177 if (!LiveIn && !LiveOut) in update()
183 << ColIdx << ": LiveIn=" << LiveIn in update()
186 ActiveCols[ColIdx].LiveIn = LiveIn; in update()
236 (!AfterInst && ActiveCols[ColIdx].LiveIn)) in printAfterOtherLine()
292 if (ActiveCols[ColIdx2].isActive() && ActiveCols[ColIdx2].LiveIn) in printBetweenInsts()
323 else if (ActiveCols[ColIdx].LiveIn && ActiveCols[ColIdx].LiveOut) in printAfterInst()
[all …]
H A DSourcePrinter.h46 bool LiveIn = false; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp55 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs) in isLiveInSExt() local
56 if (LiveIn.first == VReg) in isLiveInSExt()
57 return LiveIn.second.isSExt(); in isLiveInSExt()
62 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs) in isLiveInZExt() local
63 if (LiveIn.first == VReg) in isLiveInZExt()
64 return LiveIn.second.isZExt(); in isLiveInZExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeCalc.cpp61 LiveIn.clear(); in reset()
66 for (const LiveInBlock &I : LiveIn) { in updateFromLiveIns()
86 LiveIn.clear(); in updateFromLiveIns()
270 LiveIn.clear(); in findReachingDefs()
313 LiveIn.reserve(WorkList.size()); in findReachingDefs()
321 LiveIn.back().Kill = Use; in findReachingDefs()
339 for (LiveInBlock &I : LiveIn) { in updateSSA()
H A DRDFLiveness.cpp859 RefMap LiveIn; in computeLiveIns() local
860 traverse(&MF.front(), LiveIn); in computeLiveIns()
929 BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs()); in resetKills() local
930 CopyLiveIns(B, LiveIn); in resetKills()
982 void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { in traverse() argument
1030 LiveIn[S.first].insert(S.second.begin(), S.second.end()); in traverse()
1045 RefMap LiveInCopy = LiveIn; in traverse()
1046 LiveIn.clear(); in traverse()
1050 NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled. in traverse()
1114 emptify(LiveIn); in traverse()
[all …]
H A DStackColoring.cpp426 BitVector LiveIn; member
580 dumpBV("LIVE_IN", BlockInfo.LiveIn); in dumpBB()
842 if (LocalLiveIn.test(BlockInfo.LiveIn)) { in calculateLocalLiveness()
844 BlockInfo.LiveIn |= LocalLiveIn; in calculateLocalLiveness()
872 for (int pos = MBBLiveness.LiveIn.find_first(); pos != -1; in calculateLiveIntervals()
873 pos = MBBLiveness.LiveIn.find_next(pos)) { in calculateLiveIntervals()
H A DSplitKit.cpp255 BI.LiveIn = LVI->start <= Start; in calcLiveBlockInfo()
258 if (!BI.LiveIn) { in calcLiveBlockInfo()
285 BI.LiveIn = false; in calcLiveBlockInfo()
1570 if (BI.LiveIn && BI.LiveOut) in shouldSplitSingleBlock()
1720 assert(BI.LiveIn && "Must be live-in"); in splitRegInBlock()
1810 << (BI.LiveIn ? ", stack-in" : ", defined in block")); in splitRegOutBlock()
1818 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) { in splitRegOutBlock()
1867 << (LiveIn ? "live in" : "dead in") << ", " in print()
H A DMachineCSE.cpp707 auto LiveIn = PhysDefs.pop_back_val(); in ProcessBlockCSE() local
708 if (!MBB->isLiveIn(LiveIn.second)) in ProcessBlockCSE()
709 MBB->addLiveIn(LiveIn.second); in ProcessBlockCSE()
H A DBranchRelaxation.cpp455 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : Succ->liveins()) in fixupUnconditionalBranch() local
456 BranchBB->addLiveIn(LiveIn); in fixupUnconditionalBranch()
H A DRegAllocGreedy.cpp1261 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()
1275 if (BI.LiveIn) { in addSplitConstraints()
1482 if (BI.LiveIn && BI.LiveOut && BI.FirstDef) in calcSpillCost()
1641 if (EnableAdvancedRASplitCost && Cand.Intf.hasInterference() && BI.LiveIn && in calcGlobalSplitCost()
1662 if (BI.LiveIn) in calcGlobalSplitCost()
1737 if (BI.LiveIn) { in splitAroundRegion()
2186 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr; in calcGapWeights()
2367 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; in tryLocalSplit()
2461 bool LiveBefore = BestBefore != 0 || BI.LiveIn; in tryLocalSplit()
H A DMIRPrinter.cpp327 yaml::MachineFunctionLiveIn LiveIn; in convert() local
328 printRegMIR(LI.first, LiveIn.Register, TRI); in convert()
330 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); in convert()
331 MF.LiveIns.push_back(LiveIn); in convert()
H A DRegisterPressure.cpp918 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask; in advance() local
919 if (LiveIn.any()) { in advance()
920 discoverLiveIn(RegisterMaskPair(Reg, LiveIn)); in advance()
921 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn); in advance()
922 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn)); in advance()
H A DSplitKit.h127 bool LiveIn; ///< Current reg is live in. member
H A DMachineBasicBlock.cpp609 bool LiveIn = isLiveIn(PhysReg); in addLiveIn() local
615 if (LiveIn) in addLiveIn()
628 if (!LiveIn) in addLiveIn()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h126 SmallVector<LiveInBlock, 16> LiveIn; variable
246 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DRDFLiveness.h161 void traverse(MachineBasicBlock *B, RefMap &LiveIn);
H A DMIRYamlMapping.h223 static void mapping(IO &YamlIO, MachineFunctionLiveIn &LiveIn) {
224 YamlIO.mapRequired("reg", LiveIn.Register);
226 "virtual-reg", LiveIn.VirtualRegister,
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DStackLifetime.h44 : Begin(Size), End(Size), LiveIn(Size), LiveOut(Size) {} in BlockLifetimeInfo()
53 BitVector LiveIn; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DStackLifetime.cpp220 if (LocalLiveIn.test(BlockInfo.LiveIn)) { in calculateLocalLiveness()
221 BlockInfo.LiveIn |= LocalLiveIn; in calculateLocalLiveness()
248 if (BlockInfo.LiveIn.test(AllocaNo)) { in calculateLiveIntervals()
297 << ", livein " << BlockInfo.LiveIn << ", liveout " in dumpBlockLiveness()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp633 Register LiveIn = MRI.getLiveInVirtReg(PhysReg); in getFunctionLiveInPhysReg() local
634 if (LiveIn) { in getFunctionLiveInPhysReg()
635 MachineInstr *Def = MRI.getVRegDef(LiveIn); in getFunctionLiveInPhysReg()
639 return LiveIn; in getFunctionLiveInPhysReg()
647 LiveIn = MF.addLiveIn(PhysReg, &RC); in getFunctionLiveInPhysReg()
649 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
652 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn) in getFunctionLiveInPhysReg()
656 return LiveIn; in getFunctionLiveInPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp602 for (const auto &LiveIn : YamlMF.LiveIns) { in parseRegisterInfo() local
604 if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error)) in parseRegisterInfo()
605 return error(Error, LiveIn.Register.SourceRange); in parseRegisterInfo()
607 if (!LiveIn.VirtualRegister.Value.empty()) { in parseRegisterInfo()
609 if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value, in parseRegisterInfo()
611 return error(Error, LiveIn.VirtualRegister.SourceRange); in parseRegisterInfo()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp243 MapVector<BasicBlock *, SetVector<Value *>> LiveIn; member
3042 checkBasicSSA(DT, Data.LiveIn[&BB], BB.getTerminator()); in checkBasicSSA()
3063 Data.LiveIn[&BB] = Data.LiveSet[&BB]; in computeLiveInValues()
3064 Data.LiveIn[&BB].set_union(Data.LiveOut[&BB]); in computeLiveInValues()
3065 Data.LiveIn[&BB].set_subtract(Data.KillSet[&BB]); in computeLiveInValues()
3066 if (!Data.LiveIn[&BB].empty()) in computeLiveInValues()
3079 assert(Data.LiveIn.count(Succ)); in computeLiveInValues()
3080 LiveOut.set_union(Data.LiveIn[Succ]); in computeLiveInValues()
3096 assert(Data.LiveIn.count(BB)); in computeLiveInValues()
3097 const SetVector<Value *> &OldLiveIn = Data.LiveIn[BB]; in computeLiveInValues()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp483 auto LiveIn = std::move(LiveInIt->second); in computeBlockPressure() local
484 RPTracker.reset(*MBB->begin(), &LiveIn); in computeBlockPressure()
H A DAMDGPULegalizerInfo.cpp2807 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue() local
2815 Register AndMaskSrc = LiveIn; in loadInputValue()
2819 AndMaskSrc = B.buildLShr(S32, LiveIn, ShiftAmt).getReg(0); in loadInputValue()
2824 B.buildCopy(DstReg, LiveIn); in loadInputValue()
4708 Register LiveIn = in legalizeTrapHsaQueuePtr() local
4710 if (!loadInputValue(LiveIn, B, AMDGPUFunctionArgInfo::QUEUE_PTR)) in legalizeTrapHsaQueuePtr()
4714 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1007 LivePhysRegs LiveIn(HRI), LiveOut(HRI); in expandPostRAPseudo() local
1056 getLiveInRegsAt(LiveIn, MI); in expandPostRAPseudo()
1057 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); in expandPostRAPseudo()
1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); in expandPostRAPseudo()

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