Searched refs:LegalVecVT (Results 1 – 2 of 2) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 296 for (MVT LegalVecVT : AllVectorVTs) { in initVPUActions() local
297 setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom); in initVPUActions()
298 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
306 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom); in initVPUActions()
308 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom); in initVPUActions()
2701 EVT LegalVecVT = getTypeToTransformTo(*DAG.getContext(), OpVecVT); in lowerToVVP() local
2733 assert(LegalVecVT.isSimple()); in lowerToVVP()
2734 return DAG.getNode(VVPOpcode, DL, LegalVecVT, Op->getOperand(0), in lowerToVVP()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 12934 EVT LegalVecVT = MVT::getVectorVT(ScalarType, LegalLanes); in PerformVQDMULHCombine() local
12945 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
12946 Inp1 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp1); in PerformVQDMULHCombine()
12947 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
12959 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
12962 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext1.getOperand(0), in PerformVQDMULHCombine()
12964 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
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