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Searched refs:L2 (Results 1 – 25 of 285) sorted by relevance

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/freebsd-13.1/crypto/openssl/crypto/ec/curve448/
H A Df_generic.c174 gf L0, L1, L2; in gf_isr() local
177 gf_mul(L2, x, L1); in gf_isr()
178 gf_sqr(L1, L2); in gf_isr()
179 gf_mul(L2, x, L1); in gf_isr()
180 gf_sqrn(L1, L2, 3); in gf_isr()
181 gf_mul(L0, L2, L1); in gf_isr()
183 gf_mul(L0, L2, L1); in gf_isr()
187 gf_mul(L2, x, L0); in gf_isr()
196 gf_sqr(L0, L2); in gf_isr()
200 gf_sqr(L2, L1); in gf_isr()
[all …]
/freebsd-13.1/lib/libc/i386/string/
H A Dstrcpy.S57 je L2
61 je L2
65 je L2
69 je L2
73 je L2
77 je L2
81 je L2
88 L2: popl %eax /* pop dst address */ label
H A Dstrcat.S67 je L2
71 je L2
75 je L2
79 je L2
83 je L2
87 je L2
91 je L2
98 L2: popl %eax /* pop destination address */ label
H A Dstrchr.S56 je L2
61 L2: label
H A Dstrrchr.S57 jne L2
59 L2: label
/freebsd-13.1/contrib/llvm-project/clang/include/clang/Basic/
H A DLinkage.h120 inline Linkage minLinkage(Linkage L1, Linkage L2) { in minLinkage() argument
121 if (L2 == VisibleNoLinkage) in minLinkage()
122 std::swap(L1, L2); in minLinkage()
124 if (L2 == InternalLinkage) in minLinkage()
126 if (L2 == UniqueExternalLinkage) in minLinkage()
129 return L1 < L2 ? L1 : L2; in minLinkage()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/ADT/
H A Dilist.h247 for (const_reference V : L2)
291 this->transferNodesFromList(L2, first, last);
293 base_list_type::splice(position, L2, first, last);
329 void splice(iterator where, iplist_impl &L2) {
330 if (!L2.empty())
331 transfer(where, L2, L2.begin(), L2.end());
336 transfer(where, L2, first, last);
339 if (first != last) transfer(where, L2, first, last);
342 splice(where, L2, iterator(N));
344 void splice(iterator where, iplist_impl &L2, pointer N) {
[all …]
H A Dsimple_ilist.h173 void cloneFrom(const simple_ilist &L2, Cloner clone, Disposer dispose) { in cloneFrom() argument
175 for (const_reference V : L2) in cloneFrom()
238 void splice(iterator I, simple_ilist &L2) { in splice() argument
239 splice(I, L2, L2.begin(), L2.end()); in splice()
243 void splice(iterator I, simple_ilist &L2, iterator Node) { in splice() argument
244 splice(I, L2, Node, std::next(Node)); in splice()
/freebsd-13.1/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
48 - reg : Address and size of L2 cache controller registers
49 - cache-size : Size of the entire L2 cache
50 - interrupts : Error interrupt of L2 controller
51 - cache-line-size : Size of L2 cache lines
55 L2: l2-cache-controller@20000 {
59 cache-size = <0x40000>; // L2,256K
/freebsd-13.1/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
178 description: disable the outer sync operation on the L2 cache.
200 L2 dynamic clock gating. Value: <0> (forcibly
[all …]
/freebsd-13.1/crypto/openssl/crypto/whrlpool/
H A Dwp_block.c580 K.q[2] = L2; in whirlpool_block()
606 S.q[2] = L2; in whirlpool_block()
615 L2 = C2(K, 0); in whirlpool_block()
624 L2 ^= C1(K, 1); in whirlpool_block()
632 L2 ^= C0(K, 2); in whirlpool_block()
648 L2 ^= C7(K, 3); in whirlpool_block()
656 L2 ^= C6(K, 4); in whirlpool_block()
664 L2 ^= C5(K, 5); in whirlpool_block()
672 L2 ^= C4(K, 6); in whirlpool_block()
688 K.q[2] = L2; in whirlpool_block()
[all …]
/freebsd-13.1/sys/contrib/device-tree/src/arm/
H A Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
H A Dvexpress-v2p-ca9.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
H A Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
H A Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
H A Dvf610.dtsi9 next-level-cache = <&L2>;
13 L2: cache-controller@40006000 { label
/freebsd-13.1/libexec/rtld-elf/arm/
H A Drtld_start.S44 ldr sl, .L2
45 ldr r5, .L2+4
46 ldr r0, .L2+8
66 .L2: label
/freebsd-13.1/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/freebsd-13.1/sys/contrib/device-tree/Bindings/arm/calxeda/
H A Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
/freebsd-13.1/sys/dev/iavf/
H A Diavf_common.c599 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
600 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
601 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
604 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
605 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
608 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
609 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
610 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
611 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
612 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/freebsd-13.1/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_rfgain.c128 uint32_t L1, L2, L3, L4; in ar5212InvalidGainReadback() local
133 L2 = 107; in ar5212InvalidGainReadback()
137 L2 = 83; in ar5212InvalidGainReadback()
145 L2 = (gStep == 0x3f) ? 50 : gStep + 4; in ar5212InvalidGainReadback()
155 return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4)); in ar5212InvalidGainReadback()
/freebsd-13.1/lib/msun/ld80/
H A Dk_expl.h55 L2 = -3.2819649005320973e-13, /* -0x1718432a1b0e26.0p-94 */ variable
229 r = x - fn * L1 - fn * L2; /* r = r1 + r2 done independently. */ in __k_expl()
235 r2 = fn * -L2; in __k_expl()
/freebsd-13.1/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
/freebsd-13.1/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbaikal,bt1-l2-ctl.yaml8 title: Baikal-T1 L2-cache Control Block
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
17 L2-cache controller block is responsible for the tuning. Its DT node is
/freebsd-13.1/sys/contrib/device-tree/Bindings/riscv/
H A Dsifive-l2-cache.txt1 SiFive L2 Cache Controller
26 - reg: Physical base address and size of L2 cache controller registers map
32 - memory-region: reference to the reserved-memory for the L2 Loosely Integrated

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