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Searched refs:IsVGPR (Results 1 – 3 of 3) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2517 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_GLOBAL_VALUE() local
2518 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32)); in selectG_GLOBAL_VALUE()
2519 if (IsVGPR) in selectG_GLOBAL_VALUE()
2523 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); in selectG_GLOBAL_VALUE()
2536 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_PTRMASK() local
2540 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; in selectG_PTRMASK()
2542 = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass; in selectG_PTRMASK()
H A DSIInsertWaitcnts.cpp1118 const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg()); in generateWaitcntInstBefore() local
1120 if (IsVGPR) { in generateWaitcntInstBefore()
H A DSIInstrInfo.cpp3860 const bool IsVGPR = RI.hasVGPRs(RC); in verifyInstruction() local
3861 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC); in verifyInstruction()
3862 if ((IsVGPR || IsAGPR) && MO.getSubReg()) { in verifyInstruction()