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Searched refs:IsSignExt (Results 1 – 3 of 3) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local
6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine()
6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine()
6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local
8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH()
8537 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local
13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine()
13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()