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Searched refs:IsLE (Results 1 – 18 of 18) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Object/
H A DDecompressor.cpp21 bool IsLE, bool Is64Bit) { in create() argument
27 : D.consumeCompressedZLibHeader(Is64Bit, IsLE); in create()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Object/
H A DDecompressor.h28 bool IsLE, bool Is64Bit);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3622 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3626 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3631 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3632 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
[all …]
H A DMipsInstrInfo.td236 def IsLE : Predicate<"Subtarget->isLittle()">;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h619 bool &Swap, bool IsLE);
640 bool &Swap, bool IsLE);
660 unsigned &InsertAtByte, bool &Swap, bool IsLE);
H A DPPCISelLowering.cpp1780 if (IsLE) in isVPKUHUMShuffleMask()
1786 if (!IsLE) in isVPKUHUMShuffleMask()
1792 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask()
1811 if (IsLE) in isVPKUWUMShuffleMask()
1818 if (!IsLE) in isVPKUWUMShuffleMask()
1825 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask()
1853 if (IsLE) in isVPKUDUMShuffleMask()
1862 if (!IsLE) in isVPKUDUMShuffleMask()
1871 unsigned j = IsLE ? 0 : 4; in isVPKUDUMShuffleMask()
2272 if (IsLE) { in isXXSLDWIShuffleMask()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DMachOEmitter.cpp331 makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { in makeRelocationInfo() argument
335 if (IsLE) in makeRelocationInfo()
H A DELFEmitter.cpp1985 bool IsLE = Doc.Header.Data == ELFYAML::ELF_ELFDATA(ELF::ELFDATA2LSB); in yaml2elf() local
1988 if (IsLE) in yaml2elf()
1992 if (IsLE) in yaml2elf()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td218 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
H A DARMInstrThumb.td1629 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1631 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1633 Requires<[IsThumb, IsThumb1Only, IsLE]>;
H A DARMInstrNEON.td2462 let Predicates = [IsLE,HasNEON] in {
2487 let Predicates = [IsLE,HasNEON] in {
7531 let Predicates = [IsLE,HasNEON] in {
8025 let Predicates = [HasNEON,IsLE] in {
8050 let Predicates = [HasNEON,IsLE] in {
H A DARMInstrMVE.td7201 let Predicates = [HasMVEInt, IsLE] in {
7360 let Predicates = [IsLE,HasMVEInt] in {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td2488 let Predicates = [IsLE] in {
2502 let Predicates = [IsLE] in {
2634 let Predicates = [IsLE] in {
2655 let Predicates = [IsLE] in {
2823 let Predicates = [IsLE] in {
2841 let Predicates = [IsLE] in {
3164 let Predicates = [IsLE] in {
3263 let Predicates = [IsLE] in {
3290 let Predicates = [IsLE] in {
3406 let Predicates = [IsLE] in {
[all …]
H A DAArch64SVEInstrInfo.td1748 let Predicates = [IsLE] in {
2038 let Predicates = [IsLE] in {
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp15101 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15107 if (!IsLE) in EmitPPCBuiltinExpr()
15128 Ops.push_back(IsLE ? HiLd : LoLd); in EmitPPCBuiltinExpr()
15129 Ops.push_back(IsLE ? LoLd : HiLd); in EmitPPCBuiltinExpr()
15134 if (IsLE) { in EmitPPCBuiltinExpr()
15153 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
15161 if (IsLE) { in EmitPPCBuiltinExpr()
15198 if (IsLE && Width > 1) { in EmitPPCBuiltinExpr()
15211 Result = StoreSubVec(8, NumBytes - 8, IsLE ? 0 : 1); in EmitPPCBuiltinExpr()
15217 IsLE ? (Stored >> 2) : 3 - (Stored >> 2)); in EmitPPCBuiltinExpr()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7525 bool IsLE = SI.getModule()->getDataLayout().isLittleEndian(); in splitMergedValStore() local
7532 const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); in splitMergedValStore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2936 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local
2955 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits()
2978 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits()
3767 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local
3789 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
H A DDAGCombiner.cpp17016 bool IsLE = DAG.getDataLayout().isLittleEndian(); in mergeStoresOfConstantsOrVecElts() local
17018 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in mergeStoresOfConstantsOrVecElts()
18780 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local
18783 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT()
18797 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()