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Searched refs:IsAGPR (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp222 bool IsAGPR = false; in analyzeResourceUsage() local
311 IsAGPR = true; in analyzeResourceUsage()
323 IsAGPR = true; in analyzeResourceUsage()
333 IsAGPR = true; in analyzeResourceUsage()
345 IsAGPR = true; in analyzeResourceUsage()
355 IsAGPR = true; in analyzeResourceUsage()
365 IsAGPR = true; in analyzeResourceUsage()
375 IsAGPR = true; in analyzeResourceUsage()
387 IsAGPR = true; in analyzeResourceUsage()
399 IsAGPR = true; in analyzeResourceUsage()
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H A DSIFixSGPRCopies.cpp262 bool IsAGPR = TRI->hasAGPRs(DstRC); in foldVGPRCopyIntoRegSequence() local
281 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
H A DSIRegisterInfo.cpp1061 const bool IsAGPR = !ST.hasGFX90AInsts() && hasAGPRs(RC); in buildSpillLoadStore() local
1066 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1223 if (IsAGPR) { in buildSpillLoadStore()
1267 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()
H A DSILoadStoreOptimizer.cpp924 bool IsAGPR = TRI->hasAGPRs(DataRC); in checkAndPrepareMerge() local
994 if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR) in checkAndPrepareMerge()
1002 if (IsAGPR && CI.InstClass == DS_WRITE) in checkAndPrepareMerge()
H A DSIInstrInfo.cpp3861 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC); in verifyInstruction() local
3862 if ((IsVGPR || IsAGPR) && MO.getSubReg()) { in verifyInstruction()
4747 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local
4748 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()
4751 if (IsAGPR && in isOperandLegal()
4761 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
4765 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
4771 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
H A DSIISelLowering.cpp4274 bool IsAGPR = TRI->isAGPR(MRI, DataReg); in EmitInstrWithCustomInserter() local
4276 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter()
4279 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass in EmitInstrWithCustomInserter()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1243 bool IsAGPR = Val & 512; in decodeSrcOp() local
1247 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()