| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1095 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1133 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1462 MVT IntermediateVT; in computeRegisterProperties() local
1465 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1530 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1545 IntermediateVT = RegisterEVT; in getVectorTypeBreakdown()
1578 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1579 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1603 IntermediateVT = NewVT; in getVectorTypeBreakdown()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 339 EVT IntermediateVT; in getCopyFromPartsVector() local
368 PartVT, IntermediateVT, V, CallConv); in getCopyFromPartsVector()
377 PartVT, IntermediateVT, V, CallConv); in getCopyFromPartsVector()
383 IntermediateVT.isVector() in getCopyFromPartsVector()
385 *DAG.getContext(), IntermediateVT.getScalarType(), in getCopyFromPartsVector()
386 IntermediateVT.getVectorElementCount() * NumParts) in getCopyFromPartsVector()
388 IntermediateVT.getScalarType(), in getCopyFromPartsVector()
390 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
693 EVT IntermediateVT; in getCopyToPartsVector() local
716 if (IntermediateVT.isVector()) in getCopyToPartsVector()
[all …]
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| H A D | SelectionDAG.cpp | 2167 EVT IntermediateVT; in getReducedAlign() local
2170 TLI->getVectorTypeBreakdown(*getContext(), VT, IntermediateVT, in getReducedAlign()
2172 Ty = IntermediateVT.getTypeForEVT(*getContext()); in getReducedAlign()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 301 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | MipsISelLowering.cpp | 130 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
134 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 43 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | SIISelLowering.cpp | 976 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
987 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
994 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1002 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1010 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1017 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1024 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 973 EVT &IntermediateVT,
981 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
983 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1395 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | X86ISelLowering.cpp | 2190 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
2199 IntermediateVT = MVT::i1; in getVectorTypeBreakdownForCallingConv()
2208 IntermediateVT = MVT::v32i1; in getVectorTypeBreakdownForCallingConv()
2213 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, in getVectorTypeBreakdownForCallingConv()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8394 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector() local
8415 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
8419 IntermediateVT.getVectorNumElements()); in LowerINT_TO_FPVector()
8421 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
8424 Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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