| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 395 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local 396 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT() 397 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
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| H A D | TargetLowering.h | 2090 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 444 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local 446 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo() 448 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo() 449 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
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| H A D | FastISel.cpp | 304 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local 305 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant() 313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant() 1634 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local 1635 if (!TLI.isTypeLegal(IntVT)) in selectFNeg() 1638 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg() 1644 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg() 1645 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg() 1649 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
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| H A D | LegalizeDAG.cpp | 1565 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local 1566 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN() 1576 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN() 1591 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN() 1619 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local 1622 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG() 1624 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG() 1644 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local 4211 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in ConvertNodeToLibcall() local 4213 ++IntVT) { in ConvertNodeToLibcall() [all …]
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| H A D | TargetLowering.cpp | 6707 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local 6708 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT() 6710 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT() 6711 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT() 6712 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT() 6717 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT() 6720 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT() 6724 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, in expandFP_TO_SINT() 6729 SDValue R = DAG.getNode(ISD::OR, dl, IntVT, in expandFP_TO_SINT() 7440 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits); in scalarizeVectorStore() local [all …]
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| H A D | LegalizeFloatTypes.cpp | 930 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local 931 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall() 932 ++IntVT) { in findFPToIntLibcall() 933 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
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| H A D | SelectionDAG.cpp | 6248 EVT IntVT = VT.getScalarType(); in getMemsetValue() local 6249 if (!IntVT.isInteger()) in getMemsetValue() 6250 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue() 6252 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue() 6257 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue() 6258 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
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| H A D | DAGCombiner.cpp | 12926 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR() 12927 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR() 16791 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair() 16792 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair() 16799 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); in TransformFPLoadStorePair() 22480 EVT IntVT = Int.getValueType(); in foldSignChangeInBitcast() local 22483 if (!IntVT.isInteger() || IntVT.isVector()) in foldSignChangeInBitcast() 22495 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in foldSignChangeInBitcast() 22498 SignMask = APInt::getSignMask(IntVT.getSizeInBits()); in foldSignChangeInBitcast() 22503 Int = DAG.getNode(IsFabs ? ISD::AND : ISD::XOR, DL, IntVT, Int, in foldSignChangeInBitcast() [all …]
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| H A D | SelectionDAGBuilder.cpp | 247 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local 248 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); in getCopyFromParts()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 159 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions() 161 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions() 162 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions() 179 setOperationAction(ISD::CTTZ, IntVT, Expand); in initSPUActions() 180 setOperationAction(ISD::ROTL, IntVT, Expand); in initSPUActions() 181 setOperationAction(ISD::ROTR, IntVT, Expand); in initSPUActions() 192 setOperationAction(ISD::CTLZ, IntVT, Act); in initSPUActions() 194 setOperationAction(ISD::CTPOP, IntVT, Act); in initSPUActions() 198 setOperationAction(ISD::AND, IntVT, Act); in initSPUActions() 199 setOperationAction(ISD::OR, IntVT, Act); in initSPUActions() [all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 1724 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local 4714 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local 5506 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local 5513 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() 5523 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT() 5528 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT, in lowerINSERT_VECTOR_ELT() 5531 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS); in lowerINSERT_VECTOR_ELT() 5559 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerEXTRACT_VECTOR_ELT() local 5565 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerEXTRACT_VECTOR_ELT() 6993 EVT IntVT = VT.changeTypeToInteger(); in LowerINTRINSIC_W_CHAIN() local [all …]
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| H A D | AMDGPUISelLowering.cpp | 1717 MVT IntVT = MVT::i32; in LowerDIVREM24() local 1737 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24() 1784 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 740 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local 741 if (IntVT.isValid()) { in initActions() 743 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3565 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local 3566 RegParmTypes.push_back(IntVT); in forwardMustTailParameters() 19893 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local 19902 IntVT != MVT::i32) in lowerFPToIntToFP() 19906 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP() 39943 EVT IntVT = in combineBitcastvxi1() local 39945 V = DAG.getZExtOrTrunc(V, DL, IntVT); in combineBitcastvxi1() 44386 IntVT = MVT::i32; in combineCompareEqual() 45804 if (TLI.isTypeLegal(IntVT)) { in combineLoad() 49063 EVT IntVT = BV->getValueType(0); in combineVectorCompareAndMaskUnaryOp() local [all …]
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| H A D | X86ISelDAGToDAG.cpp | 1133 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local 1134 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG() 1135 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG() 1144 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4220 MVT IntVT = VecVT.changeVectorElementTypeToInteger(); in lowerVECTOR_REVERSE() local 4249 IntVT = MVT::getVectorVT(MVT::i16, VecVT.getVectorElementCount()); in lowerVECTOR_REVERSE() 4266 !Subtarget.is64Bit() && IntVT.getVectorElementType() == MVT::i64; in lowerVECTOR_REVERSE() 4269 SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1); in lowerVECTOR_REVERSE() 4271 SplatVL = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, IntVT, VLMinus1); in lowerVECTOR_REVERSE() 4273 SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL); in lowerVECTOR_REVERSE() 4275 DAG.getNode(RISCVISD::SUB_VL, DL, IntVT, SplatVL, VID, Mask, VL); in lowerVECTOR_REVERSE()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5282 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local 5283 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT() 5286 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT() 5309 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local 5310 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT() 5311 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 970 MVT IntVT = MVT::i32; in LowerFormalArguments() local 971 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12754 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local 12759 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine() 12760 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7561 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local 7568 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()
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