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Searched refs:Insn (Results 1 – 25 of 43) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
64 Insn = in readInstruction32()
92 unsigned Insn,
102 unsigned Insn,
112 unsigned Insn,
127 unsigned Insn,
137 unsigned Insn,
157 unsigned Insn,
244 if (fieldFromInstruction(Insn, 5, 1)) { in Decode2OpInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp133 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIOARr()
134 addr |= fieldFromInstruction(Insn, 9, 2) << 4; in decodeFIOARr()
135 unsigned reg = fieldFromInstruction(Insn, 4, 5); in decodeFIOARr()
145 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIORdA()
146 addr |= fieldFromInstruction(Insn, 9, 2) << 4; in decodeFIORdA()
157 unsigned b = fieldFromInstruction(Insn, 0, 3); in decodeFIOBIT()
173 unsigned d = fieldFromInstruction(Insn, 4, 5); in decodeFRd()
213 k |= fieldFromInstruction(Insn, 0, 4); in decodeFWRdK()
214 k |= fieldFromInstruction(Insn, 6, 2) << 4; in decodeFWRdK()
242 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp54 Insn = in readInstruction32()
164 unsigned S9 = Insn & 0x1ff; in DecodeMEMrs9()
225 DstB = decodeBField(Insn); in DecodeStLImmInstruction()
230 SrcC = decodeCField(Insn); in DecodeStLImmInstruction()
232 LImm = (Insn >> 32); in DecodeStLImmInstruction()
243 SrcB = decodeBField(Insn); in DecodeLdLImmInstruction()
248 DstA = decodeAField(Insn); in DecodeLdLImmInstruction()
250 LImm = (Insn >> 32); in DecodeLdLImmInstruction()
261 DstA = decodeAField(Insn); in DecodeLdRLImmInstruction()
263 SrcB = decodeBField(Insn); in DecodeLdRLImmInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp590 uint32_t Cond = (Insn >> 28) & 0xF; in checkDecodedInstruction()
639 uint32_t Insn = in getARMInstruction() local
1898 if (!fieldFromInstruction(Insn, 23, 1)) in DecodeAddrMode2IdxInstruction()
2555 fieldFromInstruction(Insn, 4,4) != 0) in DecodeSETPANInstruction()
2558 fieldFromInstruction(Insn, 0,4) != 0) in DecodeSETPANInstruction()
4482 if(!fieldFromInstruction(Insn, 7, 1)) { in DecodeMveAddrModeQ()
4939 if (fieldFromInstruction(Insn, 4, 1)) in DecodeVLD1LN()
4944 if (fieldFromInstruction(Insn, 5, 1)) in DecodeVLD1LN()
4947 if (fieldFromInstruction(Insn, 4, 1)) in DecodeVLD1LN()
4951 if (fieldFromInstruction(Insn, 6, 1)) in DecodeVLD1LN()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp84 Insn = in readInstruction32()
101 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
109 unsigned PQ = (Insn >> PqShift) & 0x3; in PostOperandDecodeAdjust()
135 uint32_t Insn; in getInstruction() local
147 PostOperandDecodeAdjust(Instr, Insn); in getInstruction()
178 unsigned Register = (Insn >> 18) & 0x1f; in decodeRiMemoryValue()
180 unsigned Offset = (Insn & 0xffff); in decodeRiMemoryValue()
190 unsigned Register = (Insn >> 15) & 0x1f; in decodeRrMemoryValue()
192 Register = (Insn >> 10) & 0x1f; in decodeRrMemoryValue()
204 unsigned Offset = (Insn & 0x3ff); in decodeSplsValue()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1175 Insn = (Bytes[0] << 8) | Bytes[1]; in readInstruction16()
1177 Insn = (Bytes[1] << 8) | Bytes[0]; in readInstruction16()
1204 Insn = in readInstruction32()
1223 uint32_t Insn; in getInstruction() local
1754 unsigned Offset = Insn & 0xf; in DecodeMemMMImm4()
1812 unsigned Offset = Insn & 0x1F; in DecodeMemMMSPImm5Lsl2()
1828 unsigned Offset = Insn & 0x7F; in DecodeMemMMGPImm7Lsl2()
1851 Offset = SignExtend32<4>(Insn & 0xf); in DecodeMemMMReglistImm4Lsl2()
2381 int Size = (int) Insn - Pos + 1; in DecodeInsSize()
2401 switch (Insn) { in DecodeSimm9SP()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp44 SmallVectorImpl<ImmInsnModel> &Insn) { in tryToreplicateChunks() argument
68 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in tryToreplicateChunks()
81 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
96 Insn.push_back({ AArch64::MOVKXi, Imm16, in tryToreplicateChunks()
224 Insn.push_back({ AArch64::ORRXri, 0, Encoding }); in trySequenceOfOnes()
247 SmallVectorImpl<ImmInsnModel> &Insn) { in expandMOVImmSimple() argument
279 Insn.push_back({ FirstOpc, Imm16, in expandMOVImmSimple()
297 Insn.push_back({ Opc, Imm16, in expandMOVImmSimple()
331 Insn.push_back({ Opc, 0, Encoding }); in expandMOVImm()
370 Insn.push_back({ AArch64::MOVKXi, Imm16, in expandMOVImm()
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H A DAArch64ExpandImm.h29 SmallVectorImpl<ImmInsnModel> &Insn);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionPrecedenceTracking.cpp59 const Instruction *Insn) { in isPreceededBySpecialInstruction() argument
61 getFirstSpecialInstruction(Insn->getParent()); in isPreceededBySpecialInstruction()
62 return MaybeFirstSpecial && MaybeFirstSpecial->comesBefore(Insn); in isPreceededBySpecialInstruction()
84 for (const Instruction &Insn : *BB) in validate()
85 if (isSpecialInstruction(&Insn)) { in validate()
86 assert(It->second == &Insn && in validate()
130 const Instruction *Insn) const { in isSpecialInstruction()
136 return !isGuaranteedToTransferExecutionToSuccessor(Insn); in isSpecialInstruction()
140 const Instruction *Insn) const { in isSpecialInstruction()
142 if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) in isSpecialInstruction()
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H A DGuardUtils.cpp35 for (auto &Insn : *DeoptBB) { in isGuardAsWidenableBranch()
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>())) in isGuardAsWidenableBranch()
38 if (Insn.mayHaveSideEffects()) in isGuardAsWidenableBranch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) { in DecodeSrcAddrModeI() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI()
183 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII()
189 unsigned As = fieldFromInstruction(Insn, 4, 2); in DecodeSrcAddrModeII()
193 static AddrMode DecodeDstAddrMode(unsigned Insn) { in DecodeDstAddrMode() argument
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode()
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1); in DecodeDstAddrMode()
234 AddrMode SrcAM = DecodeSrcAddrModeI(Insn); in getInstructionI()
235 AddrMode DstAM = DecodeDstAddrMode(Insn); in getInstructionI()
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/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp55 CodeGenInstruction &Insn,
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping()
106 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
155 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
157 if (Insn.isCodeGenOnly || Insn.isPseudo) { in evaluateExpansion()
165 if (Insn.Operands.size() != Dag->getNumArgs()) { in evaluateExpansion()
174 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) in evaluateExpansion()
175 NumMIOperands += Insn.Operands[i].MINumOperands; in evaluateExpansion()
179 addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); in evaluateExpansion()
197 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { in evaluateExpansion()
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H A DFixedLenDecoderEmitter.cpp435 Insn.push_back(BIT_UNSET); in insnWithID()
437 Insn.push_back(bitFromBits(Bits, i)); in insnWithID()
483 const insn_t &Insn) const;
564 insn_t Insn; in Filter() local
1006 if (Insn[StartBit + i] == BIT_UNSET) in fieldFromInsn()
1009 if (Insn[StartBit + i] == BIT_TRUE) in fieldFromInsn()
1070 int64_t Val = Value(Insn[i]); in getIslands()
1377 insn_t Insn; in emitSingletonTableEntry() local
1378 insnWithID(Insn, Opc.EncodingID); in emitSingletonTableEntry()
1513 insn_t Insn; in filterProcessor() local
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h62 bool isPreceededBySpecialInstruction(const Instruction *Insn);
69 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
114 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) { in isDominatedByICFIFromSameBlock() argument
115 return isPreceededBySpecialInstruction(Insn); in isDominatedByICFIFromSameBlock()
118 bool isSpecialInstruction(const Instruction *Insn) const override;
137 bool isDominatedByMemoryWriteFromSameBlock(const Instruction *Insn) { in isDominatedByMemoryWriteFromSameBlock() argument
138 return isPreceededBySpecialInstruction(Insn); in isDominatedByMemoryWriteFromSameBlock()
141 bool isSpecialInstruction(const Instruction *Insn) const override;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp340 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
362 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrSImm()
374 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdSImm()
387 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1UImm()
396 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2()
397 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs2()
406 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2()
407 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1Rs2()
420 uint32_t Insn; in getInstruction() local
429 Insn = support::endian::read32le(Bytes.data()); in getInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
128 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
133 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
141 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
159 Insn = Make_64(Hi, Lo); in readInstruction64()
169 uint64_t Insn, Hi; in getInstruction() local
172 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
175 uint8_t InstClass = getInstClass(Insn); in getInstruction()
176 uint8_t InstMode = getInstMode(Insn); in getInstruction()
178 getInstSize(Insn) != BPF_DW && in getInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
234 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
238 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
242 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
245 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
246 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
250 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
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H A DRuntimeDyldMachOARM.h272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
275 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
279 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
280 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1724 InternalInstruction Insn; in getInstruction() local
1726 Insn.bytes = Bytes; in getInstruction()
1729 Insn.mode = fMode; in getInstruction()
1731 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) || in getInstruction()
1732 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 || in getInstruction()
1733 readOperands(&Insn)) { in getInstruction()
1738 Insn.operands = x86OperandSets[Insn.spec->operands]; in getInstruction()
1739 Insn.length = Insn.readerCursor - Insn.startLocation; in getInstruction()
1740 Size = Insn.length; in getInstruction()
1747 if (Insn.hasAdSize) in getInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp340 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte); in findPltEntries() local
343 if (Insn == 0xd503245f) { in findPltEntries()
345 Insn = support::endian::read32le(PltContents.data() + Byte + Off); in findPltEntries()
348 if ((Insn & 0x9f000000) != 0x90000000) in findPltEntries()
352 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14); in findPltEntries()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp314 uint64_t &Size, uint32_t &Insn, in readInstruction32() argument
322 Insn = IsLittleEndian in readInstruction32()
335 uint32_t Insn; in getInstruction() local
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); in getInstruction()
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); in getInstruction()
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); in getInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DGVNHoist.cpp645 Instruction *Insn = MU->getMemoryInst(); in hasMemoryUse() local
648 if (BB == OldBB && firstInBB(OldPt, Insn)) in hasMemoryUse()
654 if (firstInBB(Insn, NewPt)) in hasMemoryUse()
810 Instruction *Insn = CHI.I; in checkSafety() local
811 if (!Insn) // No instruction was inserted in this CHI. in checkSafety()
814 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths)) in checkSafety()
818 if (MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn)) in checkSafety()
819 if (safeToHoistLdSt(T, Insn, UD, K, NumBBsOnAllPaths)) in checkSafety()
H A DGuardWidening.cpp284 static bool isSupportedGuardInstruction(const Instruction *Insn) { in isSupportedGuardInstruction() argument
285 if (isGuard(Insn)) in isSupportedGuardInstruction()
287 if (WidenBranchGuards && isGuardAsWidenableBranch(Insn)) in isSupportedGuardInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td113 let TSFlags{23} = isExtendable; // Insn may be extended.
115 let TSFlags{24} = isExtended; // Insn must be extended.
317 let TSFlags{17} = isExtendable; // Insn may be extended.
319 let TSFlags{18} = isExtended; // Insn must be extended.
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp260 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
268 Insn = IsLittleEndian in readInstruction64()
285 uint64_t Insn; in getInstruction() local
288 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); in getInstruction()
294 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); in getInstruction()

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