| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1173 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1439 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
2338 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
2820 EVT FinalVT = InVT; in SplitVecOp_TruncateHelper()
3786 if (InVT.isVector()) in WidenVecRes_BITCAST()
3806 InVT = NInVT; in WidenVecRes_BITCAST()
3822 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST()
3837 if (InVT.isVector()) { in WidenVecRes_BITCAST()
3847 if (InVT.isVector()) { in WidenVecRes_BITCAST()
5536 if (InVT == NVT) in ModifyToType()
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| H A D | LegalizeTypesGeneric.cpp | 44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 340 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
346 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
1066 EVT InVT = N->getOperand(OpNo).getValueType(); in PromoteIntRes_SETCC() local
1069 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1076 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1077 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1243 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
1245 ElementCount NumElts = InVT.getVectorElementCount(); in PromoteIntRes_TRUNCATE()
4710 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
4735 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
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| H A D | SelectionDAG.cpp | 3252 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3253 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
3264 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3265 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
3280 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3281 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
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| H A D | DAGCombiner.cpp | 19501 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
19513 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && in reduceBuildVecToShuffle()
19517 InVT.getVectorElementType(), SplitSize); in reduceBuildVecToShuffle()
19520 InVT.getVectorNumElements()) { in reduceBuildVecToShuffle()
19681 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); in convertBuildVecZextToZext() local
19684 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
19694 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
20519 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
20521 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
20525 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
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| H A D | LegalizeDAG.cpp | 2107 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2108 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), in ExpandArgFPLibCall()
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| /freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 276 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) { in MergeInTypeInfo()
277 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
279 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
280 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20996 InVT = EVT::getVectorVT(Ctx, InVT, 128 / InVT.getSizeInBits()); in truncateVectorWithPACK()
21009 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithPACK()
21083 assert((InVT.is256BitVector() || InVT.is128BitVector()) && in LowerTruncateVecI1()
21121 InVT = ExtVT; in LowerTruncateVecI1()
21149 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) && in LowerTRUNCATE()
30110 if (InVT == NVT) in ExtendToType()
30816 (InVT == MVT::v4i16 || InVT == MVT::v4i8)){ in ReplaceNodeResults()
30850 InVT = getTypeToTransformTo(*DAG.getContext(), InVT); in ReplaceNodeResults()
49130 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) { in combineUIntToFP()
49172 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) { in combineSIntToFP()
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| H A D | X86InstrAVX512.td | 324 X86VectorVTInfo InVT,
329 !con((ins InVT.RC:$src1), NonTiedIns),
330 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
331 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
333 (vselect_mask InVT.KRCWM:$mask, RHS,
334 (bitconvert InVT.RC:$src1)),
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1314 MVT InVT = V.getSimpleValueType(); in Select() local
1322 if (InVT.isFixedLengthVector()) in Select()
1323 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
1329 InVT, SubVecContainerVT, Idx, TRI); in Select()
1340 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
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| H A D | RISCVISelLowering.cpp | 4409 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
4410 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3421 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
3834 EVT InVT = InOp.getValueType(); in lowerConvertToSVBool() local
3838 if (InVT == OutVT) in lowerConvertToSVBool()
10505 if (InVT.isScalableVector()) { in LowerEXTRACT_SUBVECTOR()
10534 if (InVT.isScalableVector()) { in LowerINSERT_SUBVECTOR()
17111 EVT InVT = In.getValueType(); in ReplaceExtractSubVectorResults() local
17114 if (!InVT.isScalableVector() || !InVT.isInteger()) in ReplaceExtractSubVectorResults()
18666 EVT InVT = Op.getValueType(); in getSVESafeBitCast() local
18671 InVT.isScalableVector() && TLI.isTypeLegal(InVT) && in getSVESafeBitCast()
18677 if (InVT == VT) in getSVESafeBitCast()
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| H A D | AArch64ISelDAGToDAG.cpp | 3480 EVT InVT = Node->getOperand(0).getValueType(); in Select() local
3481 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in Select()
3504 EVT InVT = Node->getOperand(1).getValueType(); in Select() local
3505 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in Select()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3375 EVT InVT = In.getValueType(); in lowerBITCAST() local
3390 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3406 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4530 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
4531 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
4541 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
5320 EVT InVT = PackedOp.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5322 unsigned FromBits = InVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5339 EVT InVT = PackedOp.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5345 DAG.getSplatVector(InVT, DL, DAG.getConstant(0, DL, InVT.getScalarType())); in lowerZERO_EXTEND_VECTOR_INREG()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2925 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
2926 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
2927 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3070 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3071 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3079 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5368 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5369 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5372 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5373 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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| H A D | PPCISelLowering.cpp | 8446 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8449 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
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