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Searched refs:INSERT_SUBVECTOR (Results 1 – 21 of 21) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h535 INSERT_SUBVECTOR, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp460 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
555 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
622 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
674 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
787 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
2499 case ISD::INSERT_SUBVECTOR: in LowerOperation()
3943 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
3963 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
4033 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR()
4244 ISD::INSERT_SUBVECTOR, DL, VecVT, Res, Lo, in lowerVECTOR_REVERSE()
[all …]
H A DRISCVISelDAGToDAG.cpp1257 case ISD::INSERT_SUBVECTOR: { in Select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp924 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1291 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1299 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
2160 case ISD::INSERT_SUBVECTOR: Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break; in SplitVectorOperand()
2399 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
2401 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
3498 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
3501 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4538 case ISD::INSERT_SUBVECTOR: Res = WidenVecOp_INSERT_SUBVECTOR(N); break; in WidenVectorOperand()
4647 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT, in WidenVecOp_EXTEND()
H A DLegalizeVectorOps.cpp1010 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1069 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
H A DSelectionDAGDumper.cpp289 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DDAGCombiner.cpp1719 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
19274 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
20165 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
20550 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
21714 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
21723 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21732 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21734 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
21766 if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { in visitINSERT_SUBVECTOR()
21778 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
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H A DSelectionDAG.cpp2872 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4120 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5939 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
6121 case ISD::INSERT_SUBVECTOR: { in getNode()
10257 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
H A DLegalizeIntegerTypes.cpp100 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
4774 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
5002 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DTargetLowering.cpp821 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1032 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
2583 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
2601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAGBuilder.cpp630 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
7172 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
H A DLegalizeDAG.cpp2971 case ISD::INSERT_SUBVECTOR: in ExpandNode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2013 setTargetDAGCombine(ISD::INSERT_SUBVECTOR); in X86TargetLowering()
6002 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
6013 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && in collectConcatOps()
6751 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetConstantBitsFromNode()
7446 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetShuffleAndZeroables()
7607 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
8065 if (Opcode == ISD::INSERT_SUBVECTOR) { in getShuffleScalarElt()
13721 case ISD::INSERT_SUBVECTOR: { in lowerShuffleAsBroadcast()
16127 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128Shuffle()
17620 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128Shuffle()
[all …]
H A DX86ISelDAGToDAG.cpp708 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
922 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
925 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
950 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
953 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp285 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
401 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom); in SITargetLowering()
402 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom); in SITargetLowering()
403 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom); in SITargetLowering()
404 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom); in SITargetLowering()
407 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom); in SITargetLowering()
408 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom); in SITargetLowering()
409 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6i32, Custom); in SITargetLowering()
410 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6f32, Custom); in SITargetLowering()
620 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
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H A DAMDGPUISelLowering.cpp1619 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1622 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp121 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
225 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
2102 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1651 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1701 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3176 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp642 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
3496 case ISD::INSERT_SUBVECTOR: { in Select()
H A DAArch64ISelLowering.cpp1157 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1201 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1262 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
4833 case ISD::INSERT_SUBVECTOR: in LowerOperation()
8496 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
17317 case ISD::INSERT_SUBVECTOR: in ReplaceNodeResults()
17919 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td691 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;