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Searched refs:HasBaseReg (Results 1 – 23 of 23) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp293 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
294 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
296 HasBaseReg = false; in PrintLeaMemReference()
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
324 if (HasBaseReg) in PrintLeaMemReference()
360 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
361 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
363 HasBaseReg = false; in PrintIntelMemReference()
374 if (HasBaseReg) { in PrintIntelMemReference()
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86ISelLowering.cpp31883 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
31905 if (AM.HasBaseReg) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp347 bool HasBaseReg = false; member
467 HasBaseReg = true; in initialMatch()
473 HasBaseReg = true; in initialMatch()
622 if (HasBaseReg && BaseRegs.empty()) { in print()
625 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1826 bool HasBaseReg) { in isAlwaysFoldable() argument
1836 if (!HasBaseReg && Scale == 1) { in isAlwaysFoldable()
1838 HasBaseReg = true; in isAlwaysFoldable()
1849 bool HasBaseReg) { in isAlwaysFoldable() argument
3404 F.HasBaseReg = true; in InsertSupplementalFormula()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h200 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
274 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
278 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
868 bool HasBaseReg = (BaseGV == nullptr); variable
917 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
H A DTargetTransformInfo.h606 bool HasBaseReg, int64_t Scale,
687 int64_t BaseOffset, bool HasBaseReg,
1487 int64_t BaseOffset, bool HasBaseReg,
1513 bool HasBaseReg, int64_t Scale,
1839 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
1841 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in isLegalAddressingMode()
1899 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
1902 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp335 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
338 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
422 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
425 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h299 bool HasBaseReg, int64_t Scale,
304 AM.HasBaseReg = HasBaseReg;
334 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
339 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2352 bool HasBaseReg = false; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp245 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp1928 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
1953 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1330 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1388 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1407 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
8882 AM.HasBaseReg = true; in performSHLPtrCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3511 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4652 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4657 AddrMode.HasBaseReg = true; in matchOperationAddr()
4668 if (AddrMode.HasBaseReg) in matchOperationAddr()
4670 AddrMode.HasBaseReg = true; in matchOperationAddr()
4805 if (!AddrMode.HasBaseReg) { in matchAddr()
4806 AddrMode.HasBaseReg = true; in matchAddr()
4811 AddrMode.HasBaseReg = false; in matchAddr()
H A DTargetLoweringBase.cpp1942 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1947 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp863 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
875 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4295 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4302 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1891 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp4179 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18387 if (!AM.HasBaseReg && Scale == 2) in isLegalT2ScaledAddressingMode()
18413 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); in isLegalT1ScaledAddressingMode()
18460 if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) in isLegalAddressingMode()
18463 if (!AM.HasBaseReg && Scale == 2) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4288 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1038 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
2077 AM.HasBaseReg = true; in canFoldInAddressingMode()
2086 AM.HasBaseReg = true; in canFoldInAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15926 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
15931 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12077 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
12084 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp933 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()