1 /*-
2 * Copyright (c) 2014-2019 Ruslan Bukin <[email protected]>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Synopsys DesignWare Mobile Storage Host Controller
33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/conf.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
48 #include <sys/proc.h>
49 #include <sys/rman.h>
50 #include <sys/queue.h>
51 #include <sys/taskqueue.h>
52
53 #include <dev/mmc/bridge.h>
54 #include <dev/mmc/mmcbrvar.h>
55 #include <dev/mmc/mmc_fdt_helpers.h>
56
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/ofw/openfirm.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61
62 #include <machine/bus.h>
63 #include <machine/cpu.h>
64 #include <machine/intr.h>
65
66 #ifdef EXT_RESOURCES
67 #include <dev/extres/clk/clk.h>
68 #endif
69
70 #include <dev/mmc/host/dwmmc_reg.h>
71 #include <dev/mmc/host/dwmmc_var.h>
72
73 #include "opt_mmccam.h"
74
75 #ifdef MMCCAM
76 #include <cam/cam.h>
77 #include <cam/cam_ccb.h>
78 #include <cam/cam_debug.h>
79 #include <cam/cam_sim.h>
80 #include <cam/cam_xpt_sim.h>
81
82 #include "mmc_sim_if.h"
83 #endif
84
85 #include "mmcbr_if.h"
86
87 #ifdef DEBUG
88 #define dprintf(fmt, args...) printf(fmt, ##args)
89 #else
90 #define dprintf(x, arg...)
91 #endif
92
93 #define READ4(_sc, _reg) \
94 bus_read_4((_sc)->res[0], _reg)
95 #define WRITE4(_sc, _reg, _val) \
96 bus_write_4((_sc)->res[0], _reg, _val)
97
98 #define DIV_ROUND_UP(n, d) howmany(n, d)
99
100 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
101 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
102 #define DWMMC_LOCK_INIT(_sc) \
103 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
104 "dwmmc", MTX_DEF)
105 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
106 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
107 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
108
109 #define PENDING_CMD 0x01
110 #define PENDING_STOP 0x02
111 #define CARD_INIT_DONE 0x04
112
113 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \
114 |SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE)
115 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \
116 |SDMMC_INTMASK_RE)
117 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \
118 |SDMMC_INTMASK_HLE)
119
120 #define DES0_DIC (1 << 1) /* Disable Interrupt on Completion */
121 #define DES0_LD (1 << 2) /* Last Descriptor */
122 #define DES0_FS (1 << 3) /* First Descriptor */
123 #define DES0_CH (1 << 4) /* second address CHained */
124 #define DES0_ER (1 << 5) /* End of Ring */
125 #define DES0_CES (1 << 30) /* Card Error Summary */
126 #define DES0_OWN (1 << 31) /* OWN */
127
128 #define DES1_BS1_MASK 0x1fff
129
130 struct idmac_desc {
131 uint32_t des0; /* control */
132 uint32_t des1; /* bufsize */
133 uint32_t des2; /* buf1 phys addr */
134 uint32_t des3; /* buf2 phys addr or next descr */
135 };
136
137 #define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc)))
138 #define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS)
139 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */
140 /*
141 * Size field in DMA descriptor is 13 bits long (up to 4095 bytes),
142 * but must be a multiple of the data bus size.Additionally, we must ensure
143 * that bus_dmamap_load() doesn't additionally fragments buffer (because it
144 * is processed with page size granularity). Thus limit fragment size to half
145 * of page.
146 * XXX switch descriptor format to array and use second buffer pointer for
147 * second half of page
148 */
149 #define IDMAC_MAX_SIZE 2048
150 /*
151 * Busdma may bounce buffers, so we must reserve 2 descriptors
152 * (on start and on end) for bounced fragments.
153 */
154 #define DWMMC_MAX_DATA (IDMAC_MAX_SIZE * (IDMAC_DESC_SEGS - 2)) / MMC_SECTOR_SIZE
155
156 static void dwmmc_next_operation(struct dwmmc_softc *);
157 static int dwmmc_setup_bus(struct dwmmc_softc *, int);
158 static int dma_done(struct dwmmc_softc *, struct mmc_command *);
159 static int dma_stop(struct dwmmc_softc *);
160 static void pio_read(struct dwmmc_softc *, struct mmc_command *);
161 static void pio_write(struct dwmmc_softc *, struct mmc_command *);
162 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present);
163
164 static struct resource_spec dwmmc_spec[] = {
165 { SYS_RES_MEMORY, 0, RF_ACTIVE },
166 { SYS_RES_IRQ, 0, RF_ACTIVE },
167 { -1, 0 }
168 };
169
170 #define HWTYPE_MASK (0x0000ffff)
171 #define HWFLAG_MASK (0xffff << 16)
172
173 static void
dwmmc_get1paddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)174 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
175 {
176
177 if (nsegs != 1)
178 panic("%s: nsegs != 1 (%d)\n", __func__, nsegs);
179 if (error != 0)
180 panic("%s: error != 0 (%d)\n", __func__, error);
181
182 *(bus_addr_t *)arg = segs[0].ds_addr;
183 }
184
185 static void
dwmmc_ring_setup(void * arg,bus_dma_segment_t * segs,int nsegs,int error)186 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
187 {
188 struct dwmmc_softc *sc;
189 int idx;
190
191 sc = arg;
192 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len);
193 if (error != 0)
194 panic("%s: error != 0 (%d)\n", __func__, error);
195
196 for (idx = 0; idx < nsegs; idx++) {
197 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH;
198 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK;
199 sc->desc_ring[idx].des2 = segs[idx].ds_addr;
200
201 if (idx == 0)
202 sc->desc_ring[idx].des0 |= DES0_FS;
203
204 if (idx == (nsegs - 1)) {
205 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH);
206 sc->desc_ring[idx].des0 |= DES0_LD;
207 }
208 wmb();
209 sc->desc_ring[idx].des0 |= DES0_OWN;
210 }
211 }
212
213 static int
dwmmc_ctrl_reset(struct dwmmc_softc * sc,int reset_bits)214 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits)
215 {
216 int reg;
217 int i;
218
219 reg = READ4(sc, SDMMC_CTRL);
220 reg |= (reset_bits);
221 WRITE4(sc, SDMMC_CTRL, reg);
222
223 /* Wait reset done */
224 for (i = 0; i < 100; i++) {
225 if (!(READ4(sc, SDMMC_CTRL) & reset_bits))
226 return (0);
227 DELAY(10);
228 }
229
230 device_printf(sc->dev, "Reset failed\n");
231
232 return (1);
233 }
234
235 static int
dma_setup(struct dwmmc_softc * sc)236 dma_setup(struct dwmmc_softc *sc)
237 {
238 int error;
239 int nidx;
240 int idx;
241
242 /*
243 * Set up TX descriptor ring, descriptors, and dma maps.
244 */
245 error = bus_dma_tag_create(
246 bus_get_dma_tag(sc->dev), /* Parent tag. */
247 4096, 0, /* alignment, boundary */
248 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
249 BUS_SPACE_MAXADDR, /* highaddr */
250 NULL, NULL, /* filter, filterarg */
251 IDMAC_DESC_SIZE, 1, /* maxsize, nsegments */
252 IDMAC_DESC_SIZE, /* maxsegsize */
253 0, /* flags */
254 NULL, NULL, /* lockfunc, lockarg */
255 &sc->desc_tag);
256 if (error != 0) {
257 device_printf(sc->dev,
258 "could not create ring DMA tag.\n");
259 return (1);
260 }
261
262 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring,
263 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
264 &sc->desc_map);
265 if (error != 0) {
266 device_printf(sc->dev,
267 "could not allocate descriptor ring.\n");
268 return (1);
269 }
270
271 error = bus_dmamap_load(sc->desc_tag, sc->desc_map,
272 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr,
273 &sc->desc_ring_paddr, 0);
274 if (error != 0) {
275 device_printf(sc->dev,
276 "could not load descriptor ring map.\n");
277 return (1);
278 }
279
280 for (idx = 0; idx < IDMAC_DESC_SEGS; idx++) {
281 sc->desc_ring[idx].des0 = DES0_CH;
282 sc->desc_ring[idx].des1 = 0;
283 nidx = (idx + 1) % IDMAC_DESC_SEGS;
284 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \
285 (nidx * sizeof(struct idmac_desc));
286 }
287 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr;
288 sc->desc_ring[idx - 1].des0 |= DES0_ER;
289
290 error = bus_dma_tag_create(
291 bus_get_dma_tag(sc->dev), /* Parent tag. */
292 8, 0, /* alignment, boundary */
293 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
294 BUS_SPACE_MAXADDR, /* highaddr */
295 NULL, NULL, /* filter, filterarg */
296 IDMAC_MAX_SIZE * IDMAC_DESC_SEGS, /* maxsize */
297 IDMAC_DESC_SEGS, /* nsegments */
298 IDMAC_MAX_SIZE, /* maxsegsize */
299 0, /* flags */
300 NULL, NULL, /* lockfunc, lockarg */
301 &sc->buf_tag);
302 if (error != 0) {
303 device_printf(sc->dev,
304 "could not create ring DMA tag.\n");
305 return (1);
306 }
307
308 error = bus_dmamap_create(sc->buf_tag, 0,
309 &sc->buf_map);
310 if (error != 0) {
311 device_printf(sc->dev,
312 "could not create TX buffer DMA map.\n");
313 return (1);
314 }
315
316 return (0);
317 }
318
319 static void
dwmmc_cmd_done(struct dwmmc_softc * sc)320 dwmmc_cmd_done(struct dwmmc_softc *sc)
321 {
322 struct mmc_command *cmd;
323 #ifdef MMCCAM
324 union ccb *ccb;
325 #endif
326
327 #ifdef MMCCAM
328 ccb = sc->ccb;
329 if (ccb == NULL)
330 return;
331 cmd = &ccb->mmcio.cmd;
332 #else
333 cmd = sc->curcmd;
334 #endif
335 if (cmd == NULL)
336 return;
337
338 if (cmd->flags & MMC_RSP_PRESENT) {
339 if (cmd->flags & MMC_RSP_136) {
340 cmd->resp[3] = READ4(sc, SDMMC_RESP0);
341 cmd->resp[2] = READ4(sc, SDMMC_RESP1);
342 cmd->resp[1] = READ4(sc, SDMMC_RESP2);
343 cmd->resp[0] = READ4(sc, SDMMC_RESP3);
344 } else {
345 cmd->resp[3] = 0;
346 cmd->resp[2] = 0;
347 cmd->resp[1] = 0;
348 cmd->resp[0] = READ4(sc, SDMMC_RESP0);
349 }
350 }
351 }
352
353 static void
dwmmc_tasklet(struct dwmmc_softc * sc)354 dwmmc_tasklet(struct dwmmc_softc *sc)
355 {
356 struct mmc_command *cmd;
357
358 cmd = sc->curcmd;
359 if (cmd == NULL)
360 return;
361
362 if (!sc->cmd_done)
363 return;
364
365 if (cmd->error != MMC_ERR_NONE || !cmd->data) {
366 dwmmc_next_operation(sc);
367 } else if (cmd->data && sc->dto_rcvd) {
368 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
369 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
370 sc->use_auto_stop) {
371 if (sc->acd_rcvd)
372 dwmmc_next_operation(sc);
373 } else {
374 dwmmc_next_operation(sc);
375 }
376 }
377 }
378
379 static void
dwmmc_intr(void * arg)380 dwmmc_intr(void *arg)
381 {
382 struct mmc_command *cmd;
383 struct dwmmc_softc *sc;
384 uint32_t reg;
385
386 sc = arg;
387
388 DWMMC_LOCK(sc);
389
390 cmd = sc->curcmd;
391
392 /* First handle SDMMC controller interrupts */
393 reg = READ4(sc, SDMMC_MINTSTS);
394 if (reg) {
395 dprintf("%s 0x%08x\n", __func__, reg);
396
397 if (reg & DWMMC_CMD_ERR_FLAGS) {
398 dprintf("cmd err 0x%08x cmd 0x%08x\n",
399 reg, cmd->opcode);
400 cmd->error = MMC_ERR_TIMEOUT;
401 }
402
403 if (reg & DWMMC_DATA_ERR_FLAGS) {
404 dprintf("data err 0x%08x cmd 0x%08x\n",
405 reg, cmd->opcode);
406 cmd->error = MMC_ERR_FAILED;
407 if (!sc->use_pio) {
408 dma_done(sc, cmd);
409 dma_stop(sc);
410 }
411 }
412
413 if (reg & SDMMC_INTMASK_CMD_DONE) {
414 dwmmc_cmd_done(sc);
415 sc->cmd_done = 1;
416 }
417
418 if (reg & SDMMC_INTMASK_ACD)
419 sc->acd_rcvd = 1;
420
421 if (reg & SDMMC_INTMASK_DTO)
422 sc->dto_rcvd = 1;
423
424 if (reg & SDMMC_INTMASK_CD) {
425 dwmmc_handle_card_present(sc,
426 READ4(sc, SDMMC_CDETECT) == 0 ? true : false);
427 }
428 }
429
430 /* Ack interrupts */
431 WRITE4(sc, SDMMC_RINTSTS, reg);
432
433 if (sc->use_pio) {
434 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) {
435 pio_read(sc, cmd);
436 }
437 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) {
438 pio_write(sc, cmd);
439 }
440 } else {
441 /* Now handle DMA interrupts */
442 reg = READ4(sc, SDMMC_IDSTS);
443 if (reg) {
444 dprintf("dma intr 0x%08x\n", reg);
445 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) {
446 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
447 SDMMC_IDINTEN_RI));
448 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
449 dma_done(sc, cmd);
450 }
451 }
452 }
453
454 dwmmc_tasklet(sc);
455
456 DWMMC_UNLOCK(sc);
457 }
458
459 static void
dwmmc_handle_card_present(struct dwmmc_softc * sc,bool is_present)460 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present)
461 {
462 bool was_present;
463
464 if (dumping || SCHEDULER_STOPPED())
465 return;
466
467 was_present = sc->child != NULL;
468
469 if (!was_present && is_present) {
470 taskqueue_enqueue_timeout(taskqueue_swi_giant,
471 &sc->card_delayed_task, -(hz / 2));
472 } else if (was_present && !is_present) {
473 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task);
474 }
475 }
476
477 static void
dwmmc_card_task(void * arg,int pending __unused)478 dwmmc_card_task(void *arg, int pending __unused)
479 {
480 struct dwmmc_softc *sc = arg;
481
482 #ifdef MMCCAM
483 mmc_cam_sim_discover(&sc->mmc_sim);
484 #else
485 DWMMC_LOCK(sc);
486
487 if (READ4(sc, SDMMC_CDETECT) == 0) {
488 if (sc->child == NULL) {
489 if (bootverbose)
490 device_printf(sc->dev, "Card inserted\n");
491
492 sc->child = device_add_child(sc->dev, "mmc", -1);
493 DWMMC_UNLOCK(sc);
494 if (sc->child) {
495 device_set_ivars(sc->child, sc);
496 (void)device_probe_and_attach(sc->child);
497 }
498 } else
499 DWMMC_UNLOCK(sc);
500 } else {
501 /* Card isn't present, detach if necessary */
502 if (sc->child != NULL) {
503 if (bootverbose)
504 device_printf(sc->dev, "Card removed\n");
505
506 DWMMC_UNLOCK(sc);
507 device_delete_child(sc->dev, sc->child);
508 sc->child = NULL;
509 } else
510 DWMMC_UNLOCK(sc);
511 }
512 #endif /* MMCCAM */
513 }
514
515 static int
parse_fdt(struct dwmmc_softc * sc)516 parse_fdt(struct dwmmc_softc *sc)
517 {
518 pcell_t dts_value[3];
519 phandle_t node;
520 uint32_t bus_hz = 0;
521 int len;
522 #ifdef EXT_RESOURCES
523 int error;
524 #endif
525
526 if ((node = ofw_bus_get_node(sc->dev)) == -1)
527 return (ENXIO);
528
529 /* Set some defaults for freq and supported mode */
530 sc->host.f_min = 400000;
531 sc->host.f_max = 200000000;
532 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
533 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
534 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host);
535
536 /* fifo-depth */
537 if ((len = OF_getproplen(node, "fifo-depth")) > 0) {
538 OF_getencprop(node, "fifo-depth", dts_value, len);
539 sc->fifo_depth = dts_value[0];
540 }
541
542 /* num-slots (Deprecated) */
543 sc->num_slots = 1;
544 if ((len = OF_getproplen(node, "num-slots")) > 0) {
545 device_printf(sc->dev, "num-slots property is deprecated\n");
546 OF_getencprop(node, "num-slots", dts_value, len);
547 sc->num_slots = dts_value[0];
548 }
549
550 /* clock-frequency */
551 if ((len = OF_getproplen(node, "clock-frequency")) > 0) {
552 OF_getencprop(node, "clock-frequency", dts_value, len);
553 bus_hz = dts_value[0];
554 }
555
556 #ifdef EXT_RESOURCES
557
558 /* IP block reset is optional */
559 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset);
560 if (error != 0 &&
561 error != ENOENT &&
562 error != ENODEV) {
563 device_printf(sc->dev, "Cannot get reset\n");
564 goto fail;
565 }
566
567 /* vmmc regulator is optional */
568 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply",
569 &sc->vmmc);
570 if (error != 0 &&
571 error != ENOENT &&
572 error != ENODEV) {
573 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n");
574 goto fail;
575 }
576
577 /* vqmmc regulator is optional */
578 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply",
579 &sc->vqmmc);
580 if (error != 0 &&
581 error != ENOENT &&
582 error != ENODEV) {
583 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n");
584 goto fail;
585 }
586
587 /* Assert reset first */
588 if (sc->hwreset != NULL) {
589 error = hwreset_assert(sc->hwreset);
590 if (error != 0) {
591 device_printf(sc->dev, "Cannot assert reset\n");
592 goto fail;
593 }
594 }
595
596 /* BIU (Bus Interface Unit clock) is optional */
597 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu);
598 if (error != 0 &&
599 error != ENOENT &&
600 error != ENODEV) {
601 device_printf(sc->dev, "Cannot get 'biu' clock\n");
602 goto fail;
603 }
604
605 if (sc->biu) {
606 error = clk_enable(sc->biu);
607 if (error != 0) {
608 device_printf(sc->dev, "cannot enable biu clock\n");
609 goto fail;
610 }
611 }
612
613 /*
614 * CIU (Controller Interface Unit clock) is mandatory
615 * if no clock-frequency property is given
616 */
617 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu);
618 if (error != 0 &&
619 error != ENOENT &&
620 error != ENODEV) {
621 device_printf(sc->dev, "Cannot get 'ciu' clock\n");
622 goto fail;
623 }
624
625 if (sc->ciu) {
626 if (bus_hz != 0) {
627 error = clk_set_freq(sc->ciu, bus_hz, 0);
628 if (error != 0)
629 device_printf(sc->dev,
630 "cannot set ciu clock to %u\n", bus_hz);
631 }
632 error = clk_enable(sc->ciu);
633 if (error != 0) {
634 device_printf(sc->dev, "cannot enable ciu clock\n");
635 goto fail;
636 }
637 clk_get_freq(sc->ciu, &sc->bus_hz);
638 }
639
640 /* Enable regulators */
641 if (sc->vmmc != NULL) {
642 error = regulator_enable(sc->vmmc);
643 if (error != 0) {
644 device_printf(sc->dev, "Cannot enable vmmc regulator\n");
645 goto fail;
646 }
647 }
648 if (sc->vqmmc != NULL) {
649 error = regulator_enable(sc->vqmmc);
650 if (error != 0) {
651 device_printf(sc->dev, "Cannot enable vqmmc regulator\n");
652 goto fail;
653 }
654 }
655
656 /* Take dwmmc out of reset */
657 if (sc->hwreset != NULL) {
658 error = hwreset_deassert(sc->hwreset);
659 if (error != 0) {
660 device_printf(sc->dev, "Cannot deassert reset\n");
661 goto fail;
662 }
663 }
664 #endif /* EXT_RESOURCES */
665
666 if (sc->bus_hz == 0) {
667 device_printf(sc->dev, "No bus speed provided\n");
668 goto fail;
669 }
670
671 return (0);
672
673 fail:
674 return (ENXIO);
675 }
676
677 int
dwmmc_attach(device_t dev)678 dwmmc_attach(device_t dev)
679 {
680 struct dwmmc_softc *sc;
681 int error;
682 int slot;
683
684 sc = device_get_softc(dev);
685
686 sc->dev = dev;
687
688 /* Why not to use Auto Stop? It save a hundred of irq per second */
689 sc->use_auto_stop = 1;
690
691 error = parse_fdt(sc);
692 if (error != 0) {
693 device_printf(dev, "Can't get FDT property.\n");
694 return (ENXIO);
695 }
696
697 DWMMC_LOCK_INIT(sc);
698
699 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) {
700 device_printf(dev, "could not allocate resources\n");
701 return (ENXIO);
702 }
703
704 /* Setup interrupt handler. */
705 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
706 NULL, dwmmc_intr, sc, &sc->intr_cookie);
707 if (error != 0) {
708 device_printf(dev, "could not setup interrupt handler.\n");
709 return (ENXIO);
710 }
711
712 device_printf(dev, "Hardware version ID is %04x\n",
713 READ4(sc, SDMMC_VERID) & 0xffff);
714
715 /* XXX: we support operation for slot index 0 only */
716 slot = 0;
717 if (sc->pwren_inverted) {
718 WRITE4(sc, SDMMC_PWREN, (0 << slot));
719 } else {
720 WRITE4(sc, SDMMC_PWREN, (1 << slot));
721 }
722
723 /* Reset all */
724 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET |
725 SDMMC_CTRL_FIFO_RESET |
726 SDMMC_CTRL_DMA_RESET)))
727 return (ENXIO);
728
729 dwmmc_setup_bus(sc, sc->host.f_min);
730
731 if (sc->fifo_depth == 0) {
732 sc->fifo_depth = 1 +
733 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff);
734 device_printf(dev, "No fifo-depth, using FIFOTH %x\n",
735 sc->fifo_depth);
736 }
737
738 if (!sc->use_pio) {
739 dma_stop(sc);
740 if (dma_setup(sc))
741 return (ENXIO);
742
743 /* Install desc base */
744 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
745
746 /* Enable DMA interrupts */
747 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
748 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |
749 SDMMC_IDINTEN_RI |
750 SDMMC_IDINTEN_TI));
751 }
752
753 /* Clear and disable interrups for a while */
754 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
755 WRITE4(sc, SDMMC_INTMASK, 0);
756
757 /* Maximum timeout */
758 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
759
760 /* Enable interrupts */
761 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
762 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE |
763 SDMMC_INTMASK_DTO |
764 SDMMC_INTMASK_ACD |
765 SDMMC_INTMASK_TXDR |
766 SDMMC_INTMASK_RXDR |
767 DWMMC_ERR_FLAGS |
768 SDMMC_INTMASK_CD));
769 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);
770
771 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc);
772 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0,
773 dwmmc_card_task, sc);
774
775 #ifdef MMCCAM
776 sc->ccb = NULL;
777 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) {
778 device_printf(dev, "cannot alloc cam sim\n");
779 dwmmc_detach(dev);
780 return (ENXIO);
781 }
782 #endif
783 /*
784 * Schedule a card detection as we won't get an interrupt
785 * if the card is inserted when we attach
786 */
787 dwmmc_card_task(sc, 0);
788 return (0);
789 }
790
791 int
dwmmc_detach(device_t dev)792 dwmmc_detach(device_t dev)
793 {
794 struct dwmmc_softc *sc;
795 int ret;
796
797 sc = device_get_softc(dev);
798
799 ret = device_delete_children(dev);
800 if (ret != 0)
801 return (ret);
802
803 taskqueue_drain(taskqueue_swi_giant, &sc->card_task);
804 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task);
805
806 if (sc->intr_cookie != NULL) {
807 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
808 if (ret != 0)
809 return (ret);
810 }
811 bus_release_resources(dev, dwmmc_spec, sc->res);
812
813 DWMMC_LOCK_DESTROY(sc);
814
815 #ifdef EXT_RESOURCES
816 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0)
817 device_printf(sc->dev, "cannot deassert reset\n");
818 if (sc->biu != NULL && clk_disable(sc->biu) != 0)
819 device_printf(sc->dev, "cannot disable biu clock\n");
820 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0)
821 device_printf(sc->dev, "cannot disable ciu clock\n");
822
823 if (sc->vmmc && regulator_disable(sc->vmmc) != 0)
824 device_printf(sc->dev, "Cannot disable vmmc regulator\n");
825 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0)
826 device_printf(sc->dev, "Cannot disable vqmmc regulator\n");
827 #endif
828
829 #ifdef MMCCAM
830 mmc_cam_sim_free(&sc->mmc_sim);
831 #endif
832
833 return (0);
834 }
835
836 static int
dwmmc_setup_bus(struct dwmmc_softc * sc,int freq)837 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq)
838 {
839 int tout;
840 int div;
841
842 if (freq == 0) {
843 WRITE4(sc, SDMMC_CLKENA, 0);
844 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
845 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
846
847 tout = 1000;
848 do {
849 if (tout-- < 0) {
850 device_printf(sc->dev, "Failed update clk\n");
851 return (1);
852 }
853 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
854
855 return (0);
856 }
857
858 WRITE4(sc, SDMMC_CLKENA, 0);
859 WRITE4(sc, SDMMC_CLKSRC, 0);
860
861 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0;
862
863 WRITE4(sc, SDMMC_CLKDIV, div);
864 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
865 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START));
866
867 tout = 1000;
868 do {
869 if (tout-- < 0) {
870 device_printf(sc->dev, "Failed to update clk\n");
871 return (1);
872 }
873 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
874
875 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP));
876 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA |
877 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START);
878
879 tout = 1000;
880 do {
881 if (tout-- < 0) {
882 device_printf(sc->dev, "Failed to enable clk\n");
883 return (1);
884 }
885 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
886
887 return (0);
888 }
889
890 static int
dwmmc_update_ios(device_t brdev,device_t reqdev)891 dwmmc_update_ios(device_t brdev, device_t reqdev)
892 {
893 struct dwmmc_softc *sc;
894 struct mmc_ios *ios;
895 uint32_t reg;
896 int ret = 0;
897
898 sc = device_get_softc(brdev);
899 ios = &sc->host.ios;
900
901 dprintf("Setting up clk %u bus_width %d, timming: %d\n",
902 ios->clock, ios->bus_width, ios->timing);
903
904 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode);
905
906 if (ios->bus_width == bus_width_8)
907 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
908 else if (ios->bus_width == bus_width_4)
909 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);
910 else
911 WRITE4(sc, SDMMC_CTYPE, 0);
912
913 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) {
914 /* XXX: take care about DDR or SDR use here */
915 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);
916 }
917
918 /* Set DDR mode */
919 reg = READ4(sc, SDMMC_UHS_REG);
920 if (ios->timing == bus_timing_uhs_ddr50 ||
921 ios->timing == bus_timing_mmc_ddr52 ||
922 ios->timing == bus_timing_mmc_hs400)
923 reg |= (SDMMC_UHS_REG_DDR);
924 else
925 reg &= ~(SDMMC_UHS_REG_DDR);
926 WRITE4(sc, SDMMC_UHS_REG, reg);
927
928 if (sc->update_ios)
929 ret = sc->update_ios(sc, ios);
930
931 dwmmc_setup_bus(sc, ios->clock);
932
933 return (ret);
934 }
935
936 static int
dma_done(struct dwmmc_softc * sc,struct mmc_command * cmd)937 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd)
938 {
939 struct mmc_data *data;
940
941 data = cmd->data;
942
943 if (data->flags & MMC_DATA_WRITE)
944 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
945 BUS_DMASYNC_POSTWRITE);
946 else
947 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
948 BUS_DMASYNC_POSTREAD);
949
950 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
951 BUS_DMASYNC_POSTWRITE);
952
953 bus_dmamap_unload(sc->buf_tag, sc->buf_map);
954
955 return (0);
956 }
957
958 static int
dma_stop(struct dwmmc_softc * sc)959 dma_stop(struct dwmmc_softc *sc)
960 {
961 int reg;
962
963 reg = READ4(sc, SDMMC_CTRL);
964 reg &= ~(SDMMC_CTRL_USE_IDMAC);
965 reg |= (SDMMC_CTRL_DMA_RESET);
966 WRITE4(sc, SDMMC_CTRL, reg);
967
968 reg = READ4(sc, SDMMC_BMOD);
969 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB);
970 reg |= (SDMMC_BMOD_SWR);
971 WRITE4(sc, SDMMC_BMOD, reg);
972
973 return (0);
974 }
975
976 static int
dma_prepare(struct dwmmc_softc * sc,struct mmc_command * cmd)977 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
978 {
979 struct mmc_data *data;
980 int err;
981 int reg;
982
983 data = cmd->data;
984
985 reg = READ4(sc, SDMMC_INTMASK);
986 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR);
987 WRITE4(sc, SDMMC_INTMASK, reg);
988 dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len);
989 err = bus_dmamap_load(sc->buf_tag, sc->buf_map,
990 data->data, data->len, dwmmc_ring_setup,
991 sc, BUS_DMA_NOWAIT);
992 if (err != 0)
993 panic("dmamap_load failed\n");
994
995 /* Ensure the device can see the desc */
996 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
997 BUS_DMASYNC_PREWRITE);
998
999 if (data->flags & MMC_DATA_WRITE)
1000 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
1001 BUS_DMASYNC_PREWRITE);
1002 else
1003 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
1004 BUS_DMASYNC_PREREAD);
1005
1006 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);
1007 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
1008 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
1009
1010 WRITE4(sc, SDMMC_FIFOTH, reg);
1011 wmb();
1012
1013 reg = READ4(sc, SDMMC_CTRL);
1014 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE);
1015 WRITE4(sc, SDMMC_CTRL, reg);
1016 wmb();
1017
1018 reg = READ4(sc, SDMMC_BMOD);
1019 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB);
1020 WRITE4(sc, SDMMC_BMOD, reg);
1021
1022 /* Start */
1023 WRITE4(sc, SDMMC_PLDMND, 1);
1024
1025 return (0);
1026 }
1027
1028 static int
pio_prepare(struct dwmmc_softc * sc,struct mmc_command * cmd)1029 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
1030 {
1031 struct mmc_data *data;
1032 int reg;
1033
1034 data = cmd->data;
1035 data->xfer_len = 0;
1036
1037 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);
1038 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
1039 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
1040
1041 WRITE4(sc, SDMMC_FIFOTH, reg);
1042 wmb();
1043
1044 return (0);
1045 }
1046
1047 static void
pio_read(struct dwmmc_softc * sc,struct mmc_command * cmd)1048 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd)
1049 {
1050 struct mmc_data *data;
1051 uint32_t *p, status;
1052
1053 if (cmd == NULL || cmd->data == NULL)
1054 return;
1055
1056 data = cmd->data;
1057 if ((data->flags & MMC_DATA_READ) == 0)
1058 return;
1059
1060 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned"));
1061 p = (uint32_t *)data->data + (data->xfer_len >> 2);
1062
1063 while (data->xfer_len < data->len) {
1064 status = READ4(sc, SDMMC_STATUS);
1065 if (status & SDMMC_STATUS_FIFO_EMPTY)
1066 break;
1067 *p++ = READ4(sc, SDMMC_DATA);
1068 data->xfer_len += 4;
1069 }
1070
1071 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR);
1072 }
1073
1074 static void
pio_write(struct dwmmc_softc * sc,struct mmc_command * cmd)1075 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd)
1076 {
1077 struct mmc_data *data;
1078 uint32_t *p, status;
1079
1080 if (cmd == NULL || cmd->data == NULL)
1081 return;
1082
1083 data = cmd->data;
1084 if ((data->flags & MMC_DATA_WRITE) == 0)
1085 return;
1086
1087 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned"));
1088 p = (uint32_t *)data->data + (data->xfer_len >> 2);
1089
1090 while (data->xfer_len < data->len) {
1091 status = READ4(sc, SDMMC_STATUS);
1092 if (status & SDMMC_STATUS_FIFO_FULL)
1093 break;
1094 WRITE4(sc, SDMMC_DATA, *p++);
1095 data->xfer_len += 4;
1096 }
1097
1098 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR);
1099 }
1100
1101 static void
dwmmc_start_cmd(struct dwmmc_softc * sc,struct mmc_command * cmd)1102 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd)
1103 {
1104 struct mmc_data *data;
1105 uint32_t blksz;
1106 uint32_t cmdr;
1107
1108 dprintf("%s\n", __func__);
1109 sc->curcmd = cmd;
1110 data = cmd->data;
1111
1112 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP)
1113 dwmmc_setup_bus(sc, sc->host.ios.clock);
1114
1115 #ifndef MMCCAM
1116 /* XXX Upper layers don't always set this */
1117 cmd->mrq = sc->req;
1118 #endif
1119 /* Begin setting up command register. */
1120
1121 cmdr = cmd->opcode;
1122
1123 dprintf("cmd->opcode 0x%08x\n", cmd->opcode);
1124
1125 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
1126 cmd->opcode == MMC_GO_IDLE_STATE ||
1127 cmd->opcode == MMC_GO_INACTIVE_STATE)
1128 cmdr |= SDMMC_CMD_STOP_ABORT;
1129 else if (cmd->opcode != MMC_SEND_STATUS && data)
1130 cmdr |= SDMMC_CMD_WAIT_PRVDATA;
1131
1132 /* Set up response handling. */
1133 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) {
1134 cmdr |= SDMMC_CMD_RESP_EXP;
1135 if (cmd->flags & MMC_RSP_136)
1136 cmdr |= SDMMC_CMD_RESP_LONG;
1137 }
1138
1139 if (cmd->flags & MMC_RSP_CRC)
1140 cmdr |= SDMMC_CMD_RESP_CRC;
1141
1142 /*
1143 * XXX: Not all platforms want this.
1144 */
1145 cmdr |= SDMMC_CMD_USE_HOLD_REG;
1146
1147 if ((sc->flags & CARD_INIT_DONE) == 0) {
1148 sc->flags |= (CARD_INIT_DONE);
1149 cmdr |= SDMMC_CMD_SEND_INIT;
1150 }
1151
1152 if (data) {
1153 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK ||
1154 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) &&
1155 sc->use_auto_stop)
1156 cmdr |= SDMMC_CMD_SEND_ASTOP;
1157
1158 cmdr |= SDMMC_CMD_DATA_EXP;
1159 if (data->flags & MMC_DATA_STREAM)
1160 cmdr |= SDMMC_CMD_MODE_STREAM;
1161 if (data->flags & MMC_DATA_WRITE)
1162 cmdr |= SDMMC_CMD_DATA_WRITE;
1163
1164 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
1165 WRITE4(sc, SDMMC_BYTCNT, data->len);
1166 blksz = (data->len < MMC_SECTOR_SIZE) ? \
1167 data->len : MMC_SECTOR_SIZE;
1168 WRITE4(sc, SDMMC_BLKSIZ, blksz);
1169
1170 if (sc->use_pio) {
1171 pio_prepare(sc, cmd);
1172 } else {
1173 dma_prepare(sc, cmd);
1174 }
1175 wmb();
1176 }
1177
1178 dprintf("cmdr 0x%08x\n", cmdr);
1179
1180 WRITE4(sc, SDMMC_CMDARG, cmd->arg);
1181 wmb();
1182 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START);
1183 };
1184
1185 static void
dwmmc_next_operation(struct dwmmc_softc * sc)1186 dwmmc_next_operation(struct dwmmc_softc *sc)
1187 {
1188 struct mmc_command *cmd;
1189 dprintf("%s\n", __func__);
1190 #ifdef MMCCAM
1191 union ccb *ccb;
1192
1193 ccb = sc->ccb;
1194 if (ccb == NULL)
1195 return;
1196 cmd = &ccb->mmcio.cmd;
1197 #else
1198 struct mmc_request *req;
1199
1200 req = sc->req;
1201 if (req == NULL)
1202 return;
1203 cmd = req->cmd;
1204 #endif
1205
1206 sc->acd_rcvd = 0;
1207 sc->dto_rcvd = 0;
1208 sc->cmd_done = 0;
1209
1210 /*
1211 * XXX: Wait until card is still busy.
1212 * We do need this to prevent data timeouts,
1213 * mostly caused by multi-block write command
1214 * followed by single-read.
1215 */
1216 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))
1217 continue;
1218
1219 if (sc->flags & PENDING_CMD) {
1220 sc->flags &= ~PENDING_CMD;
1221 dwmmc_start_cmd(sc, cmd);
1222 return;
1223 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) {
1224 sc->flags &= ~PENDING_STOP;
1225 /// XXX: What to do with this?
1226 //dwmmc_start_cmd(sc, req->stop);
1227 return;
1228 }
1229
1230 #ifdef MMCCAM
1231 sc->ccb = NULL;
1232 sc->curcmd = NULL;
1233 ccb->ccb_h.status =
1234 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1235 xpt_done(ccb);
1236 #else
1237 sc->req = NULL;
1238 sc->curcmd = NULL;
1239 req->done(req);
1240 #endif
1241 }
1242
1243 static int
dwmmc_request(device_t brdev,device_t reqdev,struct mmc_request * req)1244 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1245 {
1246 struct dwmmc_softc *sc;
1247
1248 sc = device_get_softc(brdev);
1249
1250 dprintf("%s\n", __func__);
1251
1252 DWMMC_LOCK(sc);
1253
1254 #ifdef MMCCAM
1255 sc->flags |= PENDING_CMD;
1256 #else
1257 if (sc->req != NULL) {
1258 DWMMC_UNLOCK(sc);
1259 return (EBUSY);
1260 }
1261
1262 sc->req = req;
1263 sc->flags |= PENDING_CMD;
1264 if (sc->req->stop)
1265 sc->flags |= PENDING_STOP;
1266 #endif
1267 dwmmc_next_operation(sc);
1268
1269 DWMMC_UNLOCK(sc);
1270 return (0);
1271 }
1272
1273 #ifndef MMCCAM
1274 static int
dwmmc_get_ro(device_t brdev,device_t reqdev)1275 dwmmc_get_ro(device_t brdev, device_t reqdev)
1276 {
1277
1278 dprintf("%s\n", __func__);
1279
1280 return (0);
1281 }
1282
1283 static int
dwmmc_acquire_host(device_t brdev,device_t reqdev)1284 dwmmc_acquire_host(device_t brdev, device_t reqdev)
1285 {
1286 struct dwmmc_softc *sc;
1287
1288 sc = device_get_softc(brdev);
1289
1290 DWMMC_LOCK(sc);
1291 while (sc->bus_busy)
1292 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5);
1293 sc->bus_busy++;
1294 DWMMC_UNLOCK(sc);
1295 return (0);
1296 }
1297
1298 static int
dwmmc_release_host(device_t brdev,device_t reqdev)1299 dwmmc_release_host(device_t brdev, device_t reqdev)
1300 {
1301 struct dwmmc_softc *sc;
1302
1303 sc = device_get_softc(brdev);
1304
1305 DWMMC_LOCK(sc);
1306 sc->bus_busy--;
1307 wakeup(sc);
1308 DWMMC_UNLOCK(sc);
1309 return (0);
1310 }
1311 #endif /* !MMCCAM */
1312
1313 static int
dwmmc_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)1314 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1315 {
1316 struct dwmmc_softc *sc;
1317
1318 sc = device_get_softc(bus);
1319
1320 switch (which) {
1321 default:
1322 return (EINVAL);
1323 case MMCBR_IVAR_BUS_MODE:
1324 *(int *)result = sc->host.ios.bus_mode;
1325 break;
1326 case MMCBR_IVAR_BUS_WIDTH:
1327 *(int *)result = sc->host.ios.bus_width;
1328 break;
1329 case MMCBR_IVAR_CHIP_SELECT:
1330 *(int *)result = sc->host.ios.chip_select;
1331 break;
1332 case MMCBR_IVAR_CLOCK:
1333 *(int *)result = sc->host.ios.clock;
1334 break;
1335 case MMCBR_IVAR_F_MIN:
1336 *(int *)result = sc->host.f_min;
1337 break;
1338 case MMCBR_IVAR_F_MAX:
1339 *(int *)result = sc->host.f_max;
1340 break;
1341 case MMCBR_IVAR_HOST_OCR:
1342 *(int *)result = sc->host.host_ocr;
1343 break;
1344 case MMCBR_IVAR_MODE:
1345 *(int *)result = sc->host.mode;
1346 break;
1347 case MMCBR_IVAR_OCR:
1348 *(int *)result = sc->host.ocr;
1349 break;
1350 case MMCBR_IVAR_POWER_MODE:
1351 *(int *)result = sc->host.ios.power_mode;
1352 break;
1353 case MMCBR_IVAR_VDD:
1354 *(int *)result = sc->host.ios.vdd;
1355 break;
1356 case MMCBR_IVAR_VCCQ:
1357 *(int *)result = sc->host.ios.vccq;
1358 break;
1359 case MMCBR_IVAR_CAPS:
1360 *(int *)result = sc->host.caps;
1361 break;
1362 case MMCBR_IVAR_MAX_DATA:
1363 *(int *)result = DWMMC_MAX_DATA;
1364 break;
1365 case MMCBR_IVAR_TIMING:
1366 *(int *)result = sc->host.ios.timing;
1367 break;
1368 }
1369 return (0);
1370 }
1371
1372 static int
dwmmc_write_ivar(device_t bus,device_t child,int which,uintptr_t value)1373 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1374 {
1375 struct dwmmc_softc *sc;
1376
1377 sc = device_get_softc(bus);
1378
1379 switch (which) {
1380 default:
1381 return (EINVAL);
1382 case MMCBR_IVAR_BUS_MODE:
1383 sc->host.ios.bus_mode = value;
1384 break;
1385 case MMCBR_IVAR_BUS_WIDTH:
1386 sc->host.ios.bus_width = value;
1387 break;
1388 case MMCBR_IVAR_CHIP_SELECT:
1389 sc->host.ios.chip_select = value;
1390 break;
1391 case MMCBR_IVAR_CLOCK:
1392 sc->host.ios.clock = value;
1393 break;
1394 case MMCBR_IVAR_MODE:
1395 sc->host.mode = value;
1396 break;
1397 case MMCBR_IVAR_OCR:
1398 sc->host.ocr = value;
1399 break;
1400 case MMCBR_IVAR_POWER_MODE:
1401 sc->host.ios.power_mode = value;
1402 break;
1403 case MMCBR_IVAR_VDD:
1404 sc->host.ios.vdd = value;
1405 break;
1406 case MMCBR_IVAR_TIMING:
1407 sc->host.ios.timing = value;
1408 break;
1409 case MMCBR_IVAR_VCCQ:
1410 sc->host.ios.vccq = value;
1411 break;
1412 /* These are read-only */
1413 case MMCBR_IVAR_CAPS:
1414 case MMCBR_IVAR_HOST_OCR:
1415 case MMCBR_IVAR_F_MIN:
1416 case MMCBR_IVAR_F_MAX:
1417 case MMCBR_IVAR_MAX_DATA:
1418 return (EINVAL);
1419 }
1420 return (0);
1421 }
1422
1423 #ifdef MMCCAM
1424 /* Note: this function likely belongs to the specific driver impl */
1425 static int
dwmmc_switch_vccq(device_t dev,device_t child)1426 dwmmc_switch_vccq(device_t dev, device_t child)
1427 {
1428 device_printf(dev, "This is a default impl of switch_vccq() that always fails\n");
1429 return EINVAL;
1430 }
1431
1432 static int
dwmmc_get_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)1433 dwmmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
1434 {
1435 struct dwmmc_softc *sc;
1436
1437 sc = device_get_softc(dev);
1438
1439 cts->host_ocr = sc->host.host_ocr;
1440 cts->host_f_min = sc->host.f_min;
1441 cts->host_f_max = sc->host.f_max;
1442 cts->host_caps = sc->host.caps;
1443 cts->host_max_data = DWMMC_MAX_DATA;
1444 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios));
1445
1446 return (0);
1447 }
1448
1449 static int
dwmmc_set_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)1450 dwmmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
1451 {
1452 struct dwmmc_softc *sc;
1453 struct mmc_ios *ios;
1454 struct mmc_ios *new_ios;
1455 int res;
1456
1457 sc = device_get_softc(dev);
1458 ios = &sc->host.ios;
1459
1460 new_ios = &cts->ios;
1461
1462 /* Update only requested fields */
1463 if (cts->ios_valid & MMC_CLK) {
1464 ios->clock = new_ios->clock;
1465 if (bootverbose)
1466 device_printf(sc->dev, "Clock => %d\n", ios->clock);
1467 }
1468 if (cts->ios_valid & MMC_VDD) {
1469 ios->vdd = new_ios->vdd;
1470 if (bootverbose)
1471 device_printf(sc->dev, "VDD => %d\n", ios->vdd);
1472 }
1473 if (cts->ios_valid & MMC_CS) {
1474 ios->chip_select = new_ios->chip_select;
1475 if (bootverbose)
1476 device_printf(sc->dev, "CS => %d\n", ios->chip_select);
1477 }
1478 if (cts->ios_valid & MMC_BW) {
1479 ios->bus_width = new_ios->bus_width;
1480 if (bootverbose)
1481 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width);
1482 }
1483 if (cts->ios_valid & MMC_PM) {
1484 ios->power_mode = new_ios->power_mode;
1485 if (bootverbose)
1486 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode);
1487 }
1488 if (cts->ios_valid & MMC_BT) {
1489 ios->timing = new_ios->timing;
1490 if (bootverbose)
1491 device_printf(sc->dev, "Timing => %d\n", ios->timing);
1492 }
1493 if (cts->ios_valid & MMC_BM) {
1494 ios->bus_mode = new_ios->bus_mode;
1495 if (bootverbose)
1496 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode);
1497 }
1498 if (cts->ios_valid & MMC_VCCQ) {
1499 ios->vccq = new_ios->vccq;
1500 if (bootverbose)
1501 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq);
1502 res = dwmmc_switch_vccq(sc->dev, NULL);
1503 device_printf(sc->dev, "VCCQ switch result: %d\n", res);
1504 }
1505
1506 return (dwmmc_update_ios(sc->dev, NULL));
1507 }
1508
1509 static int
dwmmc_cam_request(device_t dev,union ccb * ccb)1510 dwmmc_cam_request(device_t dev, union ccb *ccb)
1511 {
1512 struct dwmmc_softc *sc;
1513 struct ccb_mmcio *mmcio;
1514
1515 sc = device_get_softc(dev);
1516 mmcio = &ccb->mmcio;
1517
1518 DWMMC_LOCK(sc);
1519
1520 #ifdef DEBUG
1521 if (__predict_false(bootverbose)) {
1522 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1523 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
1524 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
1525 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
1526 }
1527 #endif
1528 if (mmcio->cmd.data != NULL) {
1529 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
1530 panic("data->len = %d, data->flags = %d -- something is b0rked",
1531 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
1532 }
1533 if (sc->ccb != NULL) {
1534 device_printf(sc->dev, "Controller still has an active command\n");
1535 return (EBUSY);
1536 }
1537 sc->ccb = ccb;
1538 DWMMC_UNLOCK(sc);
1539 dwmmc_request(sc->dev, NULL, NULL);
1540
1541 return (0);
1542 }
1543
1544 static void
dwmmc_cam_poll(device_t dev)1545 dwmmc_cam_poll(device_t dev)
1546 {
1547 struct dwmmc_softc *sc;
1548
1549 sc = device_get_softc(dev);
1550 dwmmc_intr(sc);
1551 }
1552 #endif /* MMCCAM */
1553
1554 static device_method_t dwmmc_methods[] = {
1555 /* Bus interface */
1556 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar),
1557 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar),
1558
1559 #ifndef MMCCAM
1560 /* mmcbr_if */
1561 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios),
1562 DEVMETHOD(mmcbr_request, dwmmc_request),
1563 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro),
1564 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host),
1565 DEVMETHOD(mmcbr_release_host, dwmmc_release_host),
1566 #endif
1567
1568 #ifdef MMCCAM
1569 /* MMCCAM interface */
1570 DEVMETHOD(mmc_sim_get_tran_settings, dwmmc_get_tran_settings),
1571 DEVMETHOD(mmc_sim_set_tran_settings, dwmmc_set_tran_settings),
1572 DEVMETHOD(mmc_sim_cam_request, dwmmc_cam_request),
1573 DEVMETHOD(mmc_sim_cam_poll, dwmmc_cam_poll),
1574
1575 DEVMETHOD(bus_add_child, bus_generic_add_child),
1576 #endif
1577
1578 DEVMETHOD_END
1579 };
1580
1581 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods,
1582 sizeof(struct dwmmc_softc));
1583