| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 834 def : CompressPat<(SUB GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
836 def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
839 def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
841 def : CompressPat<(OR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
842 (C_OR GPRC:$rs1, GPRC:$rs2)>;
844 def : CompressPat<(OR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
846 def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
849 def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
857 def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
859 def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
[all …]
|
| H A D | RISCVInstrInfoB.td | 596 : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [],
776 def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
777 (C_NOT GPRC:$rs1)>;
778 def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1),
779 (C_NEG GPRC:$rs1)>;
783 def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
784 (C_ZEXTW GPRC:$rs1)>;
|
| H A D | RISCVRegisterInfo.td | 73 // are not part of GPRC, the most restrictive register class used by the
179 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
721 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
762 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
770 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
864 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
878 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
909 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
953 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitSpilling() local
1071 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitRestore() local
1475 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in eliminateFrameIndex() local
[all …]
|
| H A D | PPCRegisterInfo.td | 301 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
309 let AltOrders = [(add (sub GPRC, R2), R2),
333 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
|
| H A D | PPCISelLowering.cpp | 11258 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
11264 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11265 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11268 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11269 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11270 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11360 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11367 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11732 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in emitProbedAlloca() local
11831 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
[all …]
|
| H A D | PPCFrameLowering.cpp | 2283 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2285 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
|
| H A D | PPCInstrVSX.td | 2661 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2663 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2665 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2667 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;
|
| H A D | PPCInstrInfo.td | 635 def gprc : RegisterOperand<GPRC> {
707 def spe4rc : RegisterOperand<GPRC> {
|