Searched refs:FirstDef (Results 1 – 6 of 6) sorted by relevance
274 MemoryAccess *FirstDef = &*Defs->begin(); in insertUse() local277 if (auto *MD = dyn_cast<MemoryDef>(FirstDef)) in insertUse()278 FirstDef = MD->getDefiningAccess(); in insertUse()280 MSSA->renamePass(MU->getBlock(), FirstDef, Visited); in insertUse()441 if (auto *MD = dyn_cast<MemoryDef>(FirstDef)) in insertDef()442 FirstDef = MD->getDefiningAccess(); in insertDef()444 MSSA->renamePass(MD->getBlock(), FirstDef, Visited); in insertDef()499 auto *FirstDef = &*Defs->begin(); in fixupDefs() local501 assert(!isa<MemoryPhi>(FirstDef) && in fixupDefs()505 assert(MSSA->dominates(NewDef, FirstDef) && in fixupDefs()[all …]
446 Value *FirstDef = SI->getOperand(0); in isPredictable() local447 auto *Inst = dyn_cast<Instruction>(FirstDef); in isPredictable()461 SeenValues.insert(FirstDef); in isPredictable()660 Value *FirstDef = Switch->getOperand(0); in getStateDefMap() local662 assert(isa<PHINode>(FirstDef) && "After select unfolding, all state " in getStateDefMap()667 Stack.push_back(dyn_cast<PHINode>(FirstDef)); in getStateDefMap()678 if (Incoming == FirstDef || isa<ConstantInt>(Incoming) || in getStateDefMap()
642 MachineRegisterInfo::def_iterator FirstDef = llvm::find_if( in scavengeVReg() local646 assert(FirstDef != MRI.def_end() && in scavengeVReg()648 MachineInstr &DefMI = *FirstDef->getParent(); in scavengeVReg()
126 SlotIndex FirstDef; ///< First non-phi valno->def, or SlotIndex(). member
261 BI.FirstDef = BI.FirstInstr; in calcLiveBlockInfo()287 BI.FirstInstr = BI.FirstDef = LVI->start; in calcLiveBlockInfo()292 if (!BI.FirstDef) in calcLiveBlockInfo()293 BI.FirstDef = LVI->start; in calcLiveBlockInfo()1866 << "1st def " << FirstDef << ", " in print()
1266 BC.ChangesValue = BI.FirstDef.isValid(); in addSplitConstraints()1482 if (BI.LiveIn && BI.LiveOut && BI.FirstDef) in calcSpillCost()