Searched refs:FeatureBits (Results 1 – 13 of 13) sorted by relevance
241 FeatureBits.flip(FB); in ToggleFeature()242 return FeatureBits; in ToggleFeature()246 FeatureBits ^= FB; in ToggleFeature()247 return FeatureBits; in ToggleFeature()253 return FeatureBits; in SetFeatureBitsTransitively()260 FeatureBits.reset(I); in ClearFeatureBitsTransitively()264 return FeatureBits; in ClearFeatureBitsTransitively()278 FeatureBits.set(FeatureEntry->Value); in ToggleFeature()289 return FeatureBits; in ToggleFeature()294 return FeatureBits; in ApplyFeatureFlag()[all …]
26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument30 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument91 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()93 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) in validate()95 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
290 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,307 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
91 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable111 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()113 FeatureBits = FeatureBits_; in setFeatureBits()119 return FeatureBits[Feature]; in hasFeature()
64 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local68 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
866 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local867 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()873 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()883 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local2548 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()2549 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()4537 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local4680 const FeatureBitset &FeatureBits = in DecodeMSRMask() local4683 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()4703 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()4711 if (!(FeatureBits[ARM::HasV8MMainlineOps])) in DecodeMSRMask()4721 if (!(FeatureBits[ARM::Feature8MSecExt])) in DecodeMSRMask()4732 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()[all …]
641 u_int32_t FeatureBits; member
206 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local207 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()208 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
617 u_int32_t FeatureBits; member
2510 sc->aac_feature_bits = le32toh(supp_info->FeatureBits); in aac_describe_controller()
474 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local475 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()476 STI.setFeatureBits(FeatureBits); in selectArch()
5434 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local5435 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()