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Searched refs:FSUB (Results 1 – 25 of 51) sorted by relevance

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/freebsd-13.1/bin/pax/
H A Doptions.c101 FSUB fsub[] = {
194 FSUB tmp; in pax_options()
371 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in pax_options()
372 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) { in pax_options()
378 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in pax_options()
1027 FSUB tmp; in cpio_options()
1193 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in cpio_options()
1194 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) in cpio_options()
1198 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in cpio_options()
1306 return(strcmp(((const FSUB *)a)->name, ((const FSUB *)b)->name)); in c_frmt()
H A Dextern.h185 extern FSUB fsub[];
208 extern FSUB *frmt;
H A Dpax.h74 typedef struct fsub FSUB; typedef
H A Dpax.c75 FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c568 FSUB *orgfrmt; in append()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def53 DAG_INSTRUCTION(FSub, 2, 1, experimental_constrained_fsub, FSUB)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h378 FSUB, enumerator
H A DTargetLowering.h2488 case ISD::FSUB: in isBinOp()
2735 assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB || in isFMADLegal()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp375 case ISD::FSUB: in LegalizeOp()
770 case ISD::FSUB: in Expand()
1332 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1336 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
H A DSelectionDAGBuilder.cpp4915 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
5052 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5069 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5094 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5100 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5165 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5191 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5197 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog2()
5260 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
5281 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
[all …]
H A DSelectionDAGBuilder.h692 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); } in visitFSub()
H A DSelectionDAGDumper.cpp256 case ISD::FSUB: return "fsub"; in getOperationName()
H A DTargetLowering.cpp2824 case ISD::FSUB: in SimplifyDemandedVectorElts()
6110 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) in getNegatedExpression()
6133 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegX, Y, Flags); in getNegatedExpression()
6142 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags); in getNegatedExpression()
6149 case ISD::FSUB: { in getNegatedExpression()
6164 return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags); in getNegatedExpression()
6795 Node->isStrictFPOpcode() ? ISD::STRICT_FSUB : ISD::FSUB, SrcVT)) in expandFP_TO_UINT()
6835 SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs); in expandFP_TO_UINT()
6848 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst)); in expandFP_TO_UINT()
6876 !isOperationLegalOrCustom(ISD::FSUB, DstVT) || in expandUINT_TO_FP()
[all …]
H A DLegalizeFloatTypes.cpp126 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1246 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
2261 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
2626 case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break; in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp2354 Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); in ExpandLegalINT_TO_FP()
3216 case ISD::FSUB: { in ExpandNode()
4284 case ISD::FSUB: in ConvertNodeToLibcall()
4662 case ISD::FSUB: in PromoteNode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
903 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
904 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
905 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
906 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
997 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h916 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
917 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp629 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
645 case ISD::FSUB: in getArithmeticInstrCost()
H A DAMDGPUISelLowering.cpp351 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
524 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering()
607 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering()
634 case ISD::FSUB: in fnegFoldsIntoOp()
2269 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2304 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
H A DAArch64SchedA57.td443 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
445 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
H A DAArch64SchedKryoDetails.td639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td40 defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td417 (instregex "FSUB(S)?$"),
475 (instregex "FSUB(S)?_rec$"),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1640 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1761 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1798 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()

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