| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 2808 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost()
2809 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getTypeBasedIntrinsicInstrCost()
2816 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss in getTypeBasedIntrinsicInstrCost()
2817 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps in getTypeBasedIntrinsicInstrCost()
2818 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd in getTypeBasedIntrinsicInstrCost()
2819 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd in getTypeBasedIntrinsicInstrCost()
2822 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss in getTypeBasedIntrinsicInstrCost()
2823 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps in getTypeBasedIntrinsicInstrCost()
2824 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd in getTypeBasedIntrinsicInstrCost()
2825 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd in getTypeBasedIntrinsicInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 914 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
915 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
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| H A D | X86.td | 341 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
343 // vector FSQRT has higher throughput than the corresponding NR code.
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| /freebsd-13.1/contrib/one-true-awk/ |
| H A D | awk.h | 140 #define FSQRT 2 macro
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| H A D | lex.c | 88 { "sqrt", FSQRT, BLTIN },
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| H A D | run.c | 1634 case FSQRT: in bltin()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 96 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 868 FSQRT, enumerator
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| H A D | BasicTTIImpl.h | 464 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1563 ISDs.push_back(ISD::FSQRT); in getTypeBasedIntrinsicInstrCost()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 498 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
595 Opcode = ISD::FSQRT; break; in mightUseCTR()
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| H A D | PPCISelLowering.h | 96 FSQRT, enumerator
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| H A D | P9InstrResources.td | 1154 FSQRT
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| H A D | PPCISelLowering.cpp | 399 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
404 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
801 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
898 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
990 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1219 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in PPCTargetLowering()
1597 case PPCISD::FSQRT: in getTargetNodeName()
12711 return DAG.getNode(PPCISD::FSQRT, SDLoc(Op), VT, Op); in getSqrtResultForDenormInput()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 550 // FDIV,FSQRT
552 // TODO: Specialize FSQRT for longer latency.
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| H A D | AArch64ISelLowering.cpp | 437 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
627 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
664 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
679 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
985 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
1285 setOperationAction(ISD::FSQRT, VT, Custom); in AArch64TargetLowering()
1549 setOperationAction(ISD::FSQRT, VT, Custom); in addTypeForFixedLengthSVE()
4802 case ISD::FSQRT: in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
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| H A D | MipsSEISelLowering.cpp | 151 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
395 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1920 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 195 case ISD::FSQRT: return "fsqrt"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 124 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1244 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2247 case ISD::FSQRT: in PromoteFloatResult()
2612 case ISD::FSQRT: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 415 case ISD::FSQRT: in LegalizeOp()
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| H A D | DAGCombiner.cpp | 1690 case ISD::FSQRT: return visitFSQRT(N); in visit()
14208 if (U->getOperand(1).getOpcode() == ISD::FSQRT && in combineRepeatedFPDivisors()
14297 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
14301 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14309 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14320 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
14323 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
14370 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0)) in visitFDIV()
14576 SDValue Sqrt = DAG.getNode(ISD::FSQRT, DL, VT, N->getOperand(0)); in visitFPOW()
14577 SDValue SqrtSqrt = DAG.getNode(ISD::FSQRT, DL, VT, Sqrt); in visitFPOW()
[all …]
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| H A D | LegalizeVectorTypes.cpp | 101 case ISD::FSQRT: in ScalarizeVectorResult()
996 case ISD::FSQRT: in SplitVectorResult()
3124 case ISD::FSQRT: in WidenVectorResult()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1727 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1752 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1804 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3057 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1596 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1641 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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