| /freebsd-13.1/contrib/one-true-awk/ |
| H A D | awk.h | 147 #define FSIN 9 macro
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| H A D | lex.c | 85 { "sin", FSIN, BLTIN },
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| H A D | run.c | 1638 case FSIN: in bltin()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 95 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 870 FSIN, enumerator
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| H A D | BasicTTIImpl.h | 1566 ISDs.push_back(ISD::FSIN); in getTypeBasedIntrinsicInstrCost()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 117 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
460 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
752 case ISD::FSIN: in LowerTrig()
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| H A D | AMDGPUISelLowering.cpp | 523 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
642 case ISD::FSIN: in fnegFoldsIntoOp()
3916 case ISD::FSIN: in performFNegCombine()
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| H A D | SIISelLowering.cpp | 526 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
589 setOperationAction(ISD::FSIN, MVT::f16, Custom); in SITargetLowering()
4555 case ISD::FSIN: in LowerOperation()
8769 case ISD::FSIN: in LowerTrig()
9538 case ISD::FSIN: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 424 case ISD::FSIN: in fp16SrcZerosHighBits()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 198 case ISD::FSIN: return "fsin"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 122 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1242 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2246 case ISD::FSIN: in PromoteFloatResult()
2611 case ISD::FSIN: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2196 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2197 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3141 case ISD::FSIN: in ExpandNode()
3948 case ISD::FSIN: in ConvertNodeToLibcall()
4725 case ISD::FSIN: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 416 case ISD::FSIN: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 100 case ISD::FSIN: in ScalarizeVectorResult()
995 case ISD::FSIN: in SplitVectorResult()
3123 case ISD::FSIN: in WidenVectorResult()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 893 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 753 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1628 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1596 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1641 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 359 setOperationAction(ISD::FSIN, VT, Expand); in AArch64TargetLowering()
435 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
567 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
568 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
592 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
593 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
594 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
983 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
1411 setOperationAction(ISD::FSIN, VT, Expand); in addTypeForNEON()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 120 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 357 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
839 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
860 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
876 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1024 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1391 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1392 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1475 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 433 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
434 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 244 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 480 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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