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Searched refs:FRINT (Results 1 – 25 of 39) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def92 DAG_FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h881 FRINT, enumerator
H A DBasicTTIImpl.h1620 ISDs.push_back(ISD::FRINT); in getTypeBasedIntrinsicInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA57.td509 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
511 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
583 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
H A DAArch64SchedTSV110.td480 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
670 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedFalkorDetails.td592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
H A DAArch64SchedExynosM3.td543 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
658 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM5.td713 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
837 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM4.td654 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
799 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedThunderX2T99.td1186 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1407 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1410 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedThunderX3T110.td1293 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1514 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1517 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedKryoDetails.td963 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
975 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
H A DAArch64SchedCyclone.td577 // FRINT(AIMNPXZ) V,V
H A DAArch64ISelLowering.cpp434 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
630 setOperationAction(ISD::FRINT, MVT::f16, Promote); in AArch64TargetLowering()
662 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); in AArch64TargetLowering()
694 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
712 setOperationAction(ISD::FRINT, MVT::f16, Legal); in AArch64TargetLowering()
982 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); in AArch64TargetLowering()
1119 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
1130 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
1281 setOperationAction(ISD::FRINT, VT, Custom); in AArch64TargetLowering()
1546 setOperationAction(ISD::FRINT, VT, Custom); in addTypeForFixedLengthSVE()
[all …]
H A DAArch64SchedA64FX.td1561 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1800 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1803 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp502 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
611 Opcode = ISD::FRINT; break; in mightUseCTR()
H A DPPCISelLowering.cpp298 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
813 setOperationAction(ISD::FRINT, VT, Expand); in PPCTargetLowering()
975 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); in PPCTargetLowering()
978 setOperationAction(ISD::FRINT, MVT::f64, Legal); in PPCTargetLowering()
981 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); in PPCTargetLowering()
984 setOperationAction(ISD::FRINT, MVT::f32, Legal); in PPCTargetLowering()
1172 setOperationAction(ISD::FRINT, MVT::f128, Legal); in PPCTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp209 case ISD::FRINT: return "frint"; in getOperationName()
H A DLegalizeFloatTypes.cpp116 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1236 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
2243 case ISD::FRINT: in PromoteFloatResult()
2608 case ISD::FRINT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp427 case ISD::FRINT: in LegalizeOp()
H A DLegalizeVectorTypes.cpp97 case ISD::FRINT: in ScalarizeVectorResult()
992 case ISD::FRINT: in SplitVectorResult()
3120 case ISD::FRINT: in WidenVectorResult()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp330 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
520 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
644 case ISD::FRINT: in fnegFoldsIntoOp()
1294 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
2287 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
3914 case ISD::FRINT: in performFNegCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp125 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
231 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) in WebAssemblyTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp148 setOperationAction(ISD::FRINT, MVT::f16, Promote); in MipsSETargetLowering()
394 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1917 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp897 setOperationAction(ISD::FRINT, VT, Expand); in initActions()

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