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Searched refs:FP_ROUND (Results 1 – 25 of 31) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1142 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 }, in getCastInstrCost()
1143 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 }, in getCastInstrCost()
1144 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 }, in getCastInstrCost()
1147 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 }, in getCastInstrCost()
1148 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 }, in getCastInstrCost()
1149 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 }, in getCastInstrCost()
1152 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 }, in getCastInstrCost()
1153 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 }, in getCastInstrCost()
1154 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 }, in getCastInstrCost()
H A DAArch64ISelLowering.cpp474 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in AArch64TargetLowering()
475 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
476 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
998 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
1288 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1323 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom); in AArch64TargetLowering()
1329 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1543 setOperationAction(ISD::FP_ROUND, VT, Custom); in addTypeForFixedLengthSVE()
3476 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
4806 case ISD::FP_ROUND: in LowerOperation()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def62 DAG_INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h814 FP_ROUND, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp107 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
825 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
873 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1053 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1775 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1885 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2268 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2510 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
2592 case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
334 return DAG.getNode(ISD::FP_ROUND, DL, in ScalarizeVecRes_FP_ROUND()
641 case ISD::FP_ROUND: in ScalarizeVectorOperand()
815 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
989 case ISD::FP_ROUND: in SplitVectorResult()
1926 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
2167 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
2878 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
3094 case ISD::FP_ROUND: in WidenVectorResult()
4559 case ISD::FP_ROUND: in WidenVectorOperand()
[all …]
H A DLegalizeVectorOps.cpp432 case ISD::FP_ROUND: in LegalizeOp()
590 case ISD::FP_ROUND: in Promote()
629 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
H A DLegalizeDAG.cpp2841 case ISD::FP_ROUND: in ExpandNode()
3195 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4234 case ISD::FP_ROUND: in ConvertNodeToLibcall()
4543 TruncOp = ISD::FP_ROUND; in PromoteNode()
4552 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4612 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1, in PromoteNode()
4673 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4696 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4712 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4735 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
H A DSelectionDAGDumper.cpp343 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp1697 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
10743 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
10769 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
14308 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
14439 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
14800 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
14847 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
14861 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
14866 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, in visitFP_EXTEND()
14881 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), in visitFP_EXTEND()
[all …]
H A DSelectionDAG.cpp1246 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL)); in getFPExtendOrRound()
4370 case ISD::FP_ROUND: { in isKnownNeverNaN()
4859 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
5477 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
5717 case ISD::FP_ROUND: in getNode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp517 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
518 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
557 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
563 {ISD::FP_ROUND, MVT::v2f64, 2}, in getCastInstrCost()
751 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
H A DARMISelLowering.cpp914 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in ARMTargetLowering()
1043 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in ARMTargetLowering()
1055 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in ARMTargetLowering()
7455 if (BV.getOperand(0).getOpcode() != ISD::FP_ROUND || in LowerBuildVectorOfFPTrunc()
7459 if (BV.getOperand(1).getOpcode() != ISD::FP_ROUND || in LowerBuildVectorOfFPTrunc()
7471 return Trunc.getOpcode() == ISD::FP_ROUND && in LowerBuildVectorOfFPTrunc()
10226 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); in LowerOperation()
15609 if (Trunc->getOpcode() != ISD::FP_ROUND) in PerformSplittingToNarrowingStores()
H A DARMISelDAGToDAG.cpp3097 if (Val1.getOpcode() == ISD::FP_ROUND || Val2.getOpcode() == ISD::FP_ROUND) in tryInsertVectorElt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp174 setTargetDAGCombine(ISD::FP_ROUND); in WebAssemblyTargetLowering()
2353 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2392 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2436 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2480 case ISD::FP_ROUND: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp220 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
222 setOperationAction(ISD::FP_ROUND, MVT::v3f32, Expand); in SITargetLowering()
224 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand); in SITargetLowering()
226 setOperationAction(ISD::FP_ROUND, MVT::v5f32, Expand); in SITargetLowering()
228 setOperationAction(ISD::FP_ROUND, MVT::v6f32, Expand); in SITargetLowering()
230 setOperationAction(ISD::FP_ROUND, MVT::v7f32, Expand); in SITargetLowering()
232 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand); in SITargetLowering()
234 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand); in SITargetLowering()
4581 case ISD::FP_ROUND: in LowerOperation()
5160 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
[all …]
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
H A DR600ISelLowering.cpp249 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1760 case ISD::FP_ROUND: { in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1729 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1757 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1758 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3062 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp981 case ISD::FP_ROUND: in PreprocessISelDAG()
995 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1207 case ISD::FP_ROUND: in PreprocessISelDAG()
1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
H A DX86TargetTransformInfo.cpp1589 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1904 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
2032 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1178 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1179 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1229 setOperationAction(ISD::FP_ROUND, VT, Custom); in PPCTargetLowering()
8604 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8685 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8982 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
10885 case ISD::FP_ROUND: in LowerOperation()
13712 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
13757 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
14190 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1813 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp592 setOperationAction(ISD::FP_ROUND, VT, Custom); in RISCVTargetLowering()
813 setOperationAction(ISD::FP_ROUND, VT, Custom); in RISCVTargetLowering()
2337 case ISD::FP_ROUND: { in LowerOperation()
6226 (In2.getOpcode() != ISD::FP_ROUND || In2.getConstantOperandVal(1) != 0)) in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td498 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;

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