| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 210 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
211 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
212 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
227 { ISD::FDIV, MVT::f32, 17 }, // divss in getArithmeticInstrCost()
228 { ISD::FDIV, MVT::v4f32, 39 }, // divps in getArithmeticInstrCost()
229 { ISD::FDIV, MVT::f64, 32 }, // divsd in getArithmeticInstrCost()
230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd in getArithmeticInstrCost()
913 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
914 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 441 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
442 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 55 DAG_INSTRUCTION(FDiv, 2, 1, experimental_constrained_fdiv, FDIV)
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 380 FDIV, enumerator
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| H A D | TargetLowering.h | 2489 case ISD::FDIV: in isBinOp()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 700 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| H A D | SelectionDAGDumper.cpp | 260 case ISD::FDIV: return "fdiv"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 84 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1208 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
2253 case ISD::FDIV: in PromoteFloatResult()
2618 case ISD::FDIV: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 377 case ISD::FDIV: in LegalizeOp()
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| H A D | SelectionDAG.cpp | 4338 case ISD::FDIV: in isKnownNeverNaN()
5465 case ISD::FDIV: in foldConstantFPMath()
5496 case ISD::FDIV: in foldConstantFPMath()
5667 case ISD::FDIV: in getNode()
7894 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV) in simplifyFPBinop()
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| H A D | LegalizeVectorTypes.cpp | 116 case ISD::FDIV: in ScalarizeVectorResult()
1025 case ISD::FDIV: in SplitVectorResult()
3045 case ISD::FDIV: in WidenVectorResult()
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| H A D | FastISel.cpp | 1717 return selectBinaryOp(I, ISD::FDIV); in selectOperator()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
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| H A D | MipsSEISelLowering.cpp | 135 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
389 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
1867 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 672 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1726 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1751 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1803 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
3055 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 657 case ISD::FDIV: in getArithmeticInstrCost()
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| H A D | AMDGPUISelLowering.cpp | 508 setOperationAction(ISD::FDIV, VT, Expand); in AMDGPUTargetLowering()
680 case ISD::FDIV: in hasSourceMods()
2160 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
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| H A D | SIISelLowering.cpp | 528 setOperationAction(ISD::FDIV, MVT::f32, Custom); in SITargetLowering()
529 setOperationAction(ISD::FDIV, MVT::f64, Custom); in SITargetLowering()
604 setOperationAction(ISD::FDIV, MVT::f16, Custom); in SITargetLowering()
4559 case ISD::FDIV: return LowerFDIV(Op, DAG); in LowerOperation()
9508 case ISD::FDIV: in isCanonicalized()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 550 // FDIV,FSQRT
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| H A D | AArch64SchedA57.td | 471 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
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| H A D | AArch64ISelLowering.cpp | 428 setOperationAction(ISD::FDIV, MVT::f128, LibCall); in AArch64TargetLowering()
622 setOperationAction(ISD::FDIV, MVT::f16, Promote); in AArch64TargetLowering()
643 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
647 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
670 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
894 setTargetDAGCombine(ISD::FDIV); in AArch64TargetLowering()
972 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
1269 setOperationAction(ISD::FDIV, VT, Custom); in AArch64TargetLowering()
1532 setOperationAction(ISD::FDIV, VT, Custom); in addTypeForFixedLengthSVE()
4784 case ISD::FDIV: in LowerOperation()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 1134 FDIV
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1789 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1596 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1640 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
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