| /freebsd-13.1/contrib/one-true-awk/ |
| H A D | awk.h | 148 #define FCOS 10 macro
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| H A D | lex.c | 56 { "cos", FCOS, BLTIN },
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| H A D | run.c | 1640 case FCOS: in bltin()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 73 DAG_FUNCTION(cos, 1, 1, experimental_constrained_cos, FCOS)
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 871 FCOS, enumerator
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| H A D | BasicTTIImpl.h | 1569 ISDs.push_back(ISD::FCOS); in getTypeBasedIntrinsicInstrCost()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 116 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
459 case ISD::FCOS: in LowerOperation()
749 case ISD::FCOS: in LowerTrig()
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| H A D | SIISelLowering.cpp | 527 setOperationAction(ISD::FCOS, MVT::f32, Custom); in SITargetLowering()
588 setOperationAction(ISD::FCOS, MVT::f16, Custom); in SITargetLowering()
4556 case ISD::FCOS: in LowerOperation()
8767 case ISD::FCOS: in LowerTrig()
9539 case ISD::FCOS: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 425 case ISD::FCOS: in fp16SrcZerosHighBits()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 200 case ISD::FCOS: return "fcos"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 82 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
1206 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break; in ExpandFloatResult()
2234 case ISD::FCOS: in PromoteFloatResult()
2598 case ISD::FCOS: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2197 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3142 case ISD::FCOS: { in ExpandNode()
3151 if (Node->getOpcode() == ISD::FCOS) in ExpandNode()
3954 case ISD::FCOS: in ConvertNodeToLibcall()
4726 case ISD::FCOS: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 417 case ISD::FCOS: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 83 case ISD::FCOS: in ScalarizeVectorResult()
977 case ISD::FCOS: in SplitVectorResult()
3112 case ISD::FCOS: in WidenVectorResult()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 893 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 754 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1629 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1634 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1639 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1596 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1642 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 358 setOperationAction(ISD::FCOS, VT, Expand); in AArch64TargetLowering()
427 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
569 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
570 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
589 setOperationAction(ISD::FCOS, MVT::f16, Promote); in AArch64TargetLowering()
590 setOperationAction(ISD::FCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
591 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
971 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
1412 setOperationAction(ISD::FCOS, VT, Expand); in addTypeForNEON()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 120 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 358 setOperationAction(ISD::FCOS, VT, Expand); in addMVEVectorTypes()
840 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
861 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
877 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
1025 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1393 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1394 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1476 setOperationAction(ISD::FCOS, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 435 setOperationAction(ISD::FCOS, MVT::f32, Expand); in MipsTargetLowering()
436 setOperationAction(ISD::FCOS, MVT::f64, Expand); in MipsTargetLowering()
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| H A D | MipsSEISelLowering.cpp | 142 setOperationAction(ISD::FCOS, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 243 setOperationAction(ISD::FCOS, VT, Expand); in initSPUActions()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 481 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
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