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Searched refs:FCOPYSIGN (Results 1 – 25 of 30) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h476 FCOPYSIGN, enumerator
H A DBasicTTIImpl.h1605 ISDs.push_back(ISD::FCOPYSIGN); in getTypeBasedIntrinsicInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp80 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; in SoftenFloatResult()
846 case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break; in SoftenFloatOperand()
1093 return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS); in SoftenFloatOp_FCOPYSIGN()
1204 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break; in ExpandFloatResult()
1773 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break; in ExpandFloatOperand()
1872 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), in ExpandFloatOp_FCOPYSIGN()
2086 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break; in PromoteFloatOperand()
2228 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break; in PromoteFloatResult()
2590 case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break; in SoftPromoteHalfResult()
2882 case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break; in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp267 case ISD::FCOPYSIGN: return "fcopysign"; in getOperationName()
H A DLegalizeVectorTypes.cpp115 case ISD::FCOPYSIGN: in ScalarizeVectorResult()
926 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break; in SplitVectorResult()
1359 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo); in SplitVecRes_FCOPYSIGN()
1360 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi); in SplitVecRes_FCOPYSIGN()
2168 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break; in SplitVectorOperand()
3078 case ISD::FCOPYSIGN: in WidenVectorResult()
4549 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break; in WidenVectorOperand()
H A DLegalizeDAG.cpp1636 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) { in ExpandFABS()
1638 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero); in ExpandFABS()
3107 case ISD::FCOPYSIGN: in ExpandNode()
4700 case ISD::FCOPYSIGN: in PromoteNode()
4711 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN); in PromoteNode()
H A DLegalizeVectorOps.cpp414 case ISD::FCOPYSIGN: in LegalizeOp()
H A DDAGCombiner.cpp1691 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); in visit()
12762 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && in visitBITCAST()
14471 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1); in visitFCOPYSIGN()
14491 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14492 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1); in visitFCOPYSIGN()
14499 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14500 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1)); in visitFCOPYSIGN()
14505 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0)); in visitFCOPYSIGN()
14827 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { in visitFP_ROUND()
14831 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, in visitFP_ROUND()
[all …]
H A DSelectionDAG.cpp4363 case ISD::FCOPYSIGN: { in isKnownNeverNaN()
5471 case ISD::FCOPYSIGN: in foldConstantFPMath()
5675 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. in getNode()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def613 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does
615 /// floating point. X and the result must have the same type. FCOPYSIGN(f32,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp548 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in NVPTXTargetLowering()
549 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand); in NVPTXTargetLowering()
550 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in NVPTXTargetLowering()
551 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in NVPTXTargetLowering()
2142 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A); in LowerFROUND64()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in R600TargetLowering()
208 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in R600TargetLowering()
H A DAMDGPUISelLowering.cpp528 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in AMDGPUTargetLowering()
2264 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2312 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1648 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1649 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1650 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp608 setOperationAction(ISD::FCOPYSIGN, VT, Legal); in RISCVTargetLowering()
807 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in RISCVTargetLowering()
864 setTargetDAGCombine(ISD::FCOPYSIGN); in RISCVTargetLowering()
2622 case ISD::FCOPYSIGN: in LowerOperation()
6212 case ISD::FCOPYSIGN: { in PerformDAGCombine()
6233 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N->getOperand(0), in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in MipsTargetLowering()
357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in MipsTargetLowering()
1220 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp834 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp426 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
573 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in AArch64TargetLowering()
574 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in AArch64TargetLowering()
576 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in AArch64TargetLowering()
578 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in AArch64TargetLowering()
659 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand); in AArch64TargetLowering()
669 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering()
970 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
1424 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in addTypeForNEON()
4860 case ISD::FCOPYSIGN: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp407 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
408 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
410 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
411 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
1084 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1085 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1221 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp230 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp242 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initSPUActions()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td500 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp831 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
1019 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in ARMTargetLowering()
1401 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in ARMTargetLowering()
1402 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in ARMTargetLowering()
1474 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in ARMTargetLowering()
10143 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp575 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in X86TargetLowering()
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in X86TargetLowering()
632 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
684 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); in X86TargetLowering()
748 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom); in X86TargetLowering()
808 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
1243 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
1541 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
22006 SDValue Adder = DAG.getNode(ISD::FCOPYSIGN, dl, VT, in LowerFROUND()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1597 ISD::FPOW, ISD::FCOPYSIGN}) { in HexagonTargetLowering()

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