| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 110 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
117 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
121 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| H A D | X86FastISel.cpp | 1097 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1099 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1103 Reg = ExtReg; in X86SelectCallAddress()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/GlSel/ |
| H A D | M68kCallLowering.cpp | 38 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
39 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
126 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
129 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 218 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
219 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
250 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
251 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 64 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
73 {MRI.getType(ExtReg)}, false) in assignValueToReg()
74 .addReg(ExtReg); in assignValueToReg()
75 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
78 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
208 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
209 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AMDGPUInstructionSelector.cpp | 2102 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2107 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2114 .addReg(ExtReg) in selectG_SZA_EXT()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 931 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
934 SrcReg1 = ExtReg; in PPCEmitCmp()
937 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
940 SrcReg2 = ExtReg; in PPCEmitCmp()
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| H A D | PPCISelLowering.cpp | 11119 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
11121 ExtReg).addReg(dest); in EmitAtomicBinary()
11123 .addReg(incr).addReg(ExtReg); in EmitAtomicBinary()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5689 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
5695 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
5992 Register ExtReg; in selectArithExtendedRegister() local
6019 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6025 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6031 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
6032 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
6041 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
6043 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
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| H A D | AArch64CallLowering.cpp | 275 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
276 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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