| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 868 switch (ExtOpc) { in getRegOffOpcode()
881 switch (ExtOpc) { in getRegOffOpcode()
955 return ExtOpc; in getRegOffOpcode()
965 switch (ExtOpc) { in getDirectRegReplacement()
1606 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExact() local
1633 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) { in replaceInstrExact()
1724 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExpr() local
1726 if (ExtOpc == Hexagon::A2_tfrsi) { in replaceInstrExpr()
1771 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) { in replaceInstrExpr()
1789 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii || in replaceInstrExpr()
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| H A D | HexagonBitSimplify.cpp | 2517 unsigned ExtOpc = 0; in simplifyExtractLow() local
2520 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2522 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2524 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2526 if (ExtOpc == 0) { in simplifyExtractLow()
2527 ExtOpc = in simplifyExtractLow()
2539 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2543 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2555 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2557 switch (ExtOpc) { in simplifyExtractLow()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 448 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
451 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
452 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
462 Opcode = ExtOpc; in buildExtOrTrunc()
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| H A D | LegalizerHelper.cpp | 2318 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2320 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2321 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2324 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1809 unsigned ExtOpc = in lowerScalarSplat() local
1811 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
3516 unsigned ExtOpc = in lowerVectorIntrinsicSplats() local
3518 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicSplats()
4848 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
4851 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
5027 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
5029 ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND in ReplaceNodeResults()
5032 Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); in ReplaceNodeResults()
6352 Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); in PerformDAGCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1927 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1930 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1932 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1944 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 704 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1235 unsigned ExtOpc = in PromoteOperand() local
1237 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
10479 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
10493 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
10495 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
10817 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
10828 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
10838 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
10857 ISD::NodeType ExtOpc) { in tryToFoldExtOfMaskedLoad() argument
10872 SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); in tryToFoldExtOfMaskedLoad()
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| H A D | TargetLowering.cpp | 4553 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
4556 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24193 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
24196 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
28671 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
43600 unsigned ExtOpc = LHS.getOpcode(); in combineShiftToPMULH() local
43601 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combineShiftToPMULH()
43602 RHS.getOpcode() != ExtOpc) in combineShiftToPMULH()
44039 if (N0.getOpcode() == ExtOpc && in combineVectorPack()
44044 if (N1.getOpcode() == ExtOpc && in combineVectorPack()
46976 unsigned ExtOpc = LHS.getOpcode(); in combinePMULH() local
46977 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combinePMULH()
[all …]
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| H A D | X86TargetTransformInfo.cpp | 2323 unsigned ExtOpc = in getCastInstrCost() local
2329 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()
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