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Searched refs:ExtOp (Results 1 – 19 of 19) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DSCCP.cpp166 Value *ExtOp = Inst.getOperand(0); in simplifyInstsInBlock() local
167 if (isa<Constant>(ExtOp) || InsertedValues.count(ExtOp)) in simplifyInstsInBlock()
169 const ValueLatticeElement &IV = Solver.getLatticeValueFor(ExtOp); in simplifyInstsInBlock()
173 auto *ZExt = new ZExtInst(ExtOp, Inst.getType(), "", &Inst); in simplifyInstsInBlock()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4484 unsigned ExtOp, TruncOp; in PromoteNode() local
4486 ExtOp = ISD::BITCAST; in PromoteNode()
4493 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4497 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
4501 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
4533 unsigned ExtOp, TruncOp; in PromoteNode() local
4536 ExtOp = ISD::BITCAST; in PromoteNode()
4539 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4542 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4588 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
[all …]
H A DDAGCombiner.cpp14744 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
14746 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1533 MachineOperand ExtOp(EV); in insertInitializer() local
1544 .add(ExtOp); in insertInitializer()
1550 .add(ExtOp); in insertInitializer()
1555 .add(ExtOp) in insertInitializer()
1561 .add(ExtOp); in insertInitializer()
1569 .add(ExtOp) in insertInitializer()
1582 .add(ExtOp) in insertInitializer()
1587 .add(ExtOp); in insertInitializer()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1760 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
1765 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
1829 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
1834 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSSE.td4990 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
4999 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5004 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5034 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
5066 SDNode ExtOp> {
5068 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5072 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
5074 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
5077 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
5079 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
[all …]
H A DX86InstrAVX512.td9550 multiclass AVX512_pmovx_patterns_base<string OpcPrefix, SDNode ExtOp> {
9553 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))),
9558 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
9561 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
9567 def : Pat<(v32i16 (ExtOp (loadv32i8 addr:$src))),
9571 def : Pat<(v16i32 (ExtOp (loadv16i8 addr:$src))),
9573 def : Pat<(v16i32 (ExtOp (loadv16i16 addr:$src))),
9576 def : Pat<(v8i64 (ExtOp (loadv8i16 addr:$src))),
9579 def : Pat<(v8i64 (ExtOp (loadv8i32 addr:$src))),
9584 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
[all …]
H A DX86ISelLowering.cpp18939 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
18942 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
39052 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
39056 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
39084 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
39088 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
39128 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local
39131 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode()
50732 unsigned ExtOp = getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineExtractSubvector() local
50733 return DAG.getNode(ExtOp, DL, VT, Ext); in combineExtractSubvector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp431 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
432 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
H A DSIISelLowering.cpp9849 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
9851 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
9852 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
9853 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp444 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local
445 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
H A DLegalizerHelper.cpp1860 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local
1862 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); in widenScalarAddSubOverflow()
1932 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local
1933 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); in widenScalarMulo()
1934 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); in widenScalarMulo()
7192 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local
7198 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); in lowerSMULH_UMULH()
7199 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); in lowerSMULH_UMULH()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3085 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3098 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3714 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3717 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3720 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3782 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3785 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3788 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3946 IntOp, ExtOp, OpNode>;
3949 IntOp, ExtOp, OpNode>;
[all …]
H A DARMISelLowering.cpp12363 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
12364 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1450 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1451 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6129 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6130 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
13908 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
13909 if (!ExtOp) in combineBVOfVecSExt()
13912 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6385 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local
6386 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp); in combineINT_TO_FP()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16355 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local
16365 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), in performSignExtendInRegCombine()
16366 ExtOp, DAG.getValueType(ExtVT)); in performSignExtendInRegCombine()
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp7155 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
7159 if (ExtOp) in packTBLDVectorList()
7160 TblOps.push_back(ExtOp); in packTBLDVectorList()