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Searched refs:DestRC (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
54 } else if (DestRC == &NVPTX::Float16RegsRegClass) { in copyPhysReg()
57 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) { in copyPhysReg()
59 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
62 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp381 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
386 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
389 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
585 if (DestRC != RC) { in ListScheduleBottomUp()
587 if (!DestRC && !NewDef) in ListScheduleBottomUp()
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
H A DScheduleDAGRRList.cpp1223 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1228 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1231 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1559 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1569 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1571 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1577 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp695 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand() local
697 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
713 if (DestRC == &AMDGPU::AGPR_32RegClass && in foldOperand()
725 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
H A DSIInstrInfo.cpp6414 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
6415 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
6555 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
6556 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
6598 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
6616 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()