| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 634 RegisterSubReg DefR(MD); in visitPHI() local
640 if (DefR.SubReg) { in visitPHI()
646 visitUsesOf(DefR.Reg); in visitPHI()
682 visitUsesOf(DefR.Reg); in visitPHI()
704 RegisterSubReg DefR(MO); in visitNonBranch() local
706 if (!DefR.Reg.isVirtual()) in visitNonBranch()
724 visitUsesOf(DefR.Reg); in visitNonBranch()
1942 RegisterSubReg DefR(MD); in evaluate() local
1943 assert(!DefR.SubReg); in evaluate()
1944 if (!DefR.Reg.isVirtual()) in evaluate()
[all …]
|
| H A D | HexagonGenMux.cpp | 108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
343 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
|
| H A D | HexagonConstExtenders.cpp | 1542 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1549 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1568 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1581 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1585 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1597 return { DefR, 0 }; in insertInitializer()
1923 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
1924 NewRegs.push_back(DefR.Reg); in replaceExtenders()
[all …]
|
| H A D | HexagonEarlyIfConv.cpp | 441 Register DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
993 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1005 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
|
| H A D | HexagonBitSimplify.cpp | 1222 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1223 if (!DefR.isVirtual()) in computeUsedBits()
1225 Pending.push_back(DefR); in computeUsedBits()
2929 unsigned DefR; member
2936 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2955 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2990 unsigned DefR) const { in isBitShuffle()
3144 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3172 Register DefR = Defs.find_first(); in processLoop() local
3173 if (!DefR.isVirtual()) in processLoop()
[all …]
|
| H A D | HexagonOptAddrMode.cpp | 97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
729 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
734 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
758 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
|
| H A D | HexagonBitTracker.cpp | 961 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
962 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
963 BT::RegisterRef PD(DefR, 0); in evaluate()
966 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
|