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Searched refs:DRC (Results 1 – 14 of 14) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
72 DRC:$T, DRC:$F),
75 DRC:$T, DRC:$F),
84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
[all …]
H A DMipsInstrFPU.td216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
H A DMipsInstrInfo.td1804 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1805 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1806 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1823 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1824 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1825 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/freebsd-13.1/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun6i-a31-drc.yaml14 The DRC (Dynamic Range Controller) allows to dynamically adjust
35 - description: The DRC interface clock
36 - description: The DRC module clock
37 - description: The DRC DRAM clock
/freebsd-13.1/sys/dev/sound/macio/
H A Dtumbler.c184 u_char DRC[2]; member
230 sizeof tumbler_initdata.DRC, /* 0x02 */
360 tumbler_write(sc, TUMBLER_DRC, tumbler_initdata.DRC); in tumbler_init()
H A Dsnapper.c194 u_char DRC[6]; member
256 sizeof snapper_initdata.DRC, /* 0x02 */
408 snapper_write(sc, SNAPPER_DRC, snapper_initdata.DRC); in snapper_init()
/freebsd-13.1/sys/contrib/device-tree/Bindings/media/
H A Dexynos4-fimc-is.txt5 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
781 switch (DRC->getID()) { in buildMux()
802 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
H A DHexagonBitSimplify.cpp933 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
934 if (!DRC) in isTransparentCopy()
937 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1484 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1485 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1492 BT.put(ImmReg, DRC); in processBlock()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td1290 class AtomicLoad<PatFrag Op, RegisterClass DRC,
1292 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1293 [(set DRC:$rd, (Op i16:$rr))]>;
1295 class AtomicStore<PatFrag Op, RegisterClass DRC,
1297 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1298 [(Op i16:$rd, DRC:$rr)]>;
1301 class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
1303 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
1305 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1920 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1922 if (!DRC->contains(Reg)) { in visitMachineOperand()
1925 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2029 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2038 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2039 if (!DRC) { in visitMachineOperand()
2044 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2046 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
H A DMachineSink.cpp279 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
280 if (SRC != DRC) in INITIALIZE_PASS_DEPENDENCY()
/freebsd-13.1/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp4667 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
4669 return DRC->contains(Reg); in isLegalRegOperand()
4679 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
4680 if (!DRC) in isLegalRegOperand()
4683 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()