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Searched refs:Cycles (Results 1 – 25 of 38) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp44 unsigned int Cycles; member
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
76 unsigned int Cycles = 0);
79 unsigned int &Cycles);
135 unsigned Cycles = I->second; in runOnMachineFunction() local
142 if (Cycles < Threshold) { in runOnMachineFunction()
168 if (Cycles >= Threshold) in findReturns()
181 findReturns(*I, Cycles); in findReturns()
196 Cycles += BBInfo.Cycles; in cyclesUntilReturn()
208 Cycles += CyclesToEnd; in cyclesUntilReturn()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) { in writeStartEvent() argument
25 CRD.Cycles = Cycles; in writeStartEvent()
26 DependentWriteCyclesLeft = Cycles; in writeStartEvent()
31 unsigned Cycles) { in writeStartEvent() argument
41 if (TotalCycles < Cycles) { in writeStartEvent()
44 CRD.Cycles = Cycles; in writeStartEvent()
45 TotalCycles = Cycles; in writeStartEvent()
132 if (CriticalRegDep.Cycles) in computeCriticalRegDep()
138 if (WriteCRD.Cycles > MaxLatency) in computeCriticalRegDep()
144 if (ReadCRD.Cycles > MaxLatency) in computeCriticalRegDep()
H A DPipeline.cpp45 ++Cycles; in run()
48 return Cycles; in run()
86 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n'); in notifyCycleBegin()
92 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n"); in notifyCycleEnd()
H A DInstrBuilder.cpp68 if (!PRE->Cycles) { in initializeUsedResources()
88 CycleSegment RCy(0, PRE->Cycles, false); in initializeUsedResources()
92 SuperResources[Super] += PRE->Cycles; in initializeUsedResources()
372 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
400 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h66 uint16_t Cycles; member
69 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
79 int16_t Cycles; member
83 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
98 int Cycles; member
102 && Cycles == Other.Cycles;
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp49 if (WLEntry->Cycles < 0) in computeInstrLatency()
50 return WLEntry->Cycles; in computeInstrLatency()
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles)); in computeInstrLatency()
95 if (!I->Cycles) in getReciprocalThroughput()
98 double Temp = NumUnits * 1.0 / I->Cycles; in getReciprocalThroughput()
163 DelayCycles = std::min(DelayCycles, E.Cycles); in getForwardingDelayCycles()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h122 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); in onGroupIssued() local
123 if (CriticalPredecessor.Cycles < Cycles) { in onGroupIssued()
125 CriticalPredecessor.Cycles = Cycles; in onGroupIssued()
187 if (isWaiting() && CriticalPredecessor.Cycles) in cycleEvent()
188 CriticalPredecessor.Cycles--; in cycleEvent()
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles) in TimelineView() argument
24 MaxCycle(Cycles == 0 ? std::numeric_limits<unsigned>::max() : Cycles), in TimelineView()
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, in tryChangeColor() argument
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize); in tryChangeColor()
257 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { in printTimelineHeader() argument
259 if (Cycles >= 10) { in printTimelineHeader()
261 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
272 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
H A DBottleneckAnalysis.cpp506 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID); in onEvent() local
513 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles); in onEvent()
519 if (RegDep.Cycles) { in onEvent()
520 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID); in onEvent()
522 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
526 if (MemDep.Cycles) { in onEvent()
527 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID); in onEvent()
529 addMemoryDep(From, To, Cycles); in onEvent()
H A DTimelineView.h167 unsigned Cycles);
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); in execute() local
41 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits))); in execute()
56 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits))); in execute()
H A DInOrderIssueStage.cpp29 void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) { in update() argument
31 CyclesLeft = Cycles; in update()
118 if (unsigned Cycles = checkRegisterHazard(PRF, STI, IR)) { in canExecute() local
119 SI.update(IR, Cycles, StallInfo::StallKind::REGISTER_DEPS); in canExecute()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp855 struct Cycles { struct
902 << Cycles{"ResLength", ResLength} in shouldConvertIf()
905 << Cycles{"CritLimit", CritLimit} in shouldConvertIf()
991 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
994 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
996 << Cycles{"CritLimit", CritLimit} << "."; in shouldConvertIf()
1009 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
1015 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
1135 unsigned Cycles = 0; in shouldConvertIf() local
1139 Cycles += NumCycles - 1; in shouldConvertIf()
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H A DTargetSchedule.cpp126 static unsigned capLatency(int Cycles) { in capLatency() argument
127 return Cycles >= 0 ? Cycles : 1000; in capLatency()
224 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency()
H A DMachineTraceMetrics.cpp130 PRCycles[PI->ProcResourceIdx] += PI->Cycles; in getResources()
583 Cycles.erase(&I); in invalidate()
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
800 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
808 InstrCycles &MICycles = Cycles[&UseMI]; in updateDepth()
1082 unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0; in computeInstrHeights()
1121 InstrCycles &MICycles = Cycles[&MI]; in computeInstrHeights()
1237 unsigned Cycles = 0; in getResourceLength() local
1247 Cycles += in getResourceLength()
1248 (PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx)); in getResourceLength()
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H A DMachineScheduler.cpp2034 RemainingCounts[PIdx] += (Factor * PI->Cycles); in init()
2094 NextUnreserved += Cycles; in getNextResourceCycleByInstance()
2103 unsigned Cycles) { in getNextResourceCycle() argument
2132 getNextResourceCycle(SC, SubUnits[I], Cycles); in getNextResourceCycle()
2192 unsigned Cycles = PE.Cycles; in checkHazard() local
2197 MaxObservedStall = std::max(Cycles, MaxObservedStall); in checkHazard()
2347 unsigned Count = Factor * Cycles; in countResource()
2349 << Cycles << "x" << Factor << "u\n"); in countResource()
2466 std::max(ReservedUntil, NextCycle + PI->Cycles); in bumpNode()
2633 ResDelta.CritResources += PI->Cycles; in initResourceDelta()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h188 unsigned Cycles; member
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
375 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
419 void subtract(unsigned Cycles) { in subtract() argument
420 assert(End >= Cycles); in subtract()
421 End -= Cycles; in subtract()
439 ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
440 : CS(Cycles), NumUnits(Units) {} in CS()
H A DPipeline.h57 unsigned Cycles; variable
65 Pipeline() : Cycles(0) {} in Pipeline()
H A DSupport.h56 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
57 : Numerator(Cycles), Denominator(ResourceUnits) {} in Numerator() argument
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp308 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
309 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
955 Cycles.push_back(Cycles[i]); in ExpandProcResources()
971 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1072 WLEntry.Cycles = 0; in GenSchedClassTables()
1103 std::vector<int64_t> Cycles = in GenSchedClassTables() local
1106 if (Cycles.empty()) { in GenSchedClassTables()
1109 Cycles.resize(PRVec.size(), 1); in GenSchedClassTables()
1128 WPREntry.Cycles = Cycles[PRIdx]; in GenSchedClassTables()
1137 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles; in GenSchedClassTables()
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/freebsd-13.1/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbaikal,bt1-l2-ctl.yaml29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp190 if (PI->Cycles > 1) in dumpSU()
191 OS << "(" << PI->Cycles << "cyc)"; in dumpSU()
304 CurrCounter += PI->Cycles; in EmitInstruction()
404 Cost = PI->Cycles; in resourcesCost()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h299 return TE.Cycles.lookup(&MI); in getInstrCycles()
325 DenseMap<const MachineInstr*, InstrCycles> Cycles; variable
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td43 // the execution of an instruction. Cycles represents the number of
52 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
59 int Cycles = cycles; // length of stage in machine cycles
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h48 void update(const InstRef &Inst, unsigned Cycles, StallKind SK);

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