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Searched refs:CreateReg (Results 1 – 25 of 67) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp245 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
257 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
268 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
381 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
398 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineOutliner.cpp826 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
832 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
H A DMachineInstr.cpp108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); in addImplicitDefUseOperands()
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); in addImplicitDefUseOperands()
1935 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2002 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2039 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp333 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
335 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp216 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
223 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h544 MachineOperand::CreateReg(PredReg, false)}};
550 return MachineOperand::CreateReg(CCReg, false);
557 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMSLSHardening.cpp332 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
H A DThumb2InstrInfo.cpp569 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
601 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp647 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
695 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
806 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
855 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
861 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
874 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
880 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
908 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
910 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
1235 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
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H A DFunctionLoweringInfo.cpp374 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
399 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h199 Register CreateReg(MVT VT, bool isDivergent = false);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp460 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp198 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon9c9a31020111::MSP430Operand
459 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp661 MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false, in emitVSETVLIs()
664 MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false, in emitVSETVLIs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp206 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonc447f3e60111::AVROperand
396 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp596 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonec9e6daa0211::VEOperand
1435 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1)); in parseOperand()
1436 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2)); in parseOperand()
1494 Op = VEOperand::CreateReg(RegNo, S, E); in parseVEAsmOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp369 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertBLRToBL()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp86 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
92 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp366 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp438 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anon967245c60211::SparcOperand
954 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
1014 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1982 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() function in __anon56f6c4660111::AArch64Operand
4113 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4132 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4149 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4164 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
5392 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
5555 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
5571 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
5588 Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
6806 Operands.push_back(AArch64Operand::CreateReg(Pair, RegKind::Scalar, S, in tryParseGPRSeqPair()
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