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Searched refs:Core (Results 1 – 25 of 178) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td19 // Core - 32-bit core registers
28 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
29 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
30 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
31 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
33 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
34 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
35 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
37 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp231 unsigned Units = ISJ.Core.getUnits(); in restrictNoSlot1Store()
236 ISJ.Core.setUnits(Units & ~Slot1Mask); in restrictNoSlot1Store()
314 ISJ.Core.setAllUnits(); in permitNonSlot()
366 if (!ISJ->Core.getUnits()) in restrictStoreLoadOrder()
385 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); in restrictStoreLoadOrder()
397 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); in restrictStoreLoadOrder()
417 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); in restrictStoreLoadOrder()
425 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); in restrictStoreLoadOrder()
571 return (I.Core.getUnits() == Slot3Mask); in restrictPreferSlot3()
589 PrefSlot3Inst->Core.setUnits(saveUnits); in restrictPreferSlot3()
[all …]
H A DHexagonShuffler.h113 HexagonResource Core; variable
120 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
127 return (HexagonResource::lessWeight(B.Core, Core));
132 return (HexagonResource::lessUnits(A.Core, B.Core)); in lessCore()
/freebsd-13.1/sys/contrib/device-tree/Bindings/mips/loongson/
H A Ddevices.yaml20 - description: Classic Loongson64 Quad Core + LS7A
24 - description: Classic Loongson64 Quad Core + RS780E
28 - description: Classic Loongson64 Octa Core + RS780E
32 - description: Generic Loongson64 Quad Core + LS7A
36 - description: Virtual Loongson64 Quad Core + VirtIO
/freebsd-13.1/lib/clang/liblldb/
H A DMakefile148 SRCS+= Core/Address.cpp
153 SRCS+= Core/Debugger.cpp
164 SRCS+= Core/IOHandler.cpp
166 SRCS+= Core/Mangled.cpp
167 SRCS+= Core/Module.cpp
169 SRCS+= Core/ModuleList.cpp
170 SRCS+= Core/Opcode.cpp
172 SRCS+= Core/Progress.cpp
175 SRCS+= Core/Section.cpp
181 SRCS+= Core/Value.cpp
[all …]
/freebsd-13.1/usr.bin/clang/lld/
H A DMakefile78 SRCS+= lib/Core/Error.cpp
79 SRCS+= lib/Core/File.cpp
80 SRCS+= lib/Core/LinkingContext.cpp
81 SRCS+= lib/Core/Reader.cpp
82 SRCS+= lib/Core/Resolver.cpp
83 SRCS+= lib/Core/SymbolTable.cpp
/freebsd-13.1/lib/clang/libclang/
H A DMakefile657 SRCS_FUL+= StaticAnalyzer/Core/APSIntType.cpp
662 SRCS_FUL+= StaticAnalyzer/Core/BugReporter.cpp
664 SRCS_FUL+= StaticAnalyzer/Core/CallEvent.cpp
665 SRCS_FUL+= StaticAnalyzer/Core/Checker.cpp
672 SRCS_FUL+= StaticAnalyzer/Core/CoreEngine.cpp
677 SRCS_FUL+= StaticAnalyzer/Core/ExprEngine.cpp
686 SRCS_FUL+= StaticAnalyzer/Core/MemRegion.cpp
694 SRCS_FUL+= StaticAnalyzer/Core/SVals.cpp
698 SRCS_FUL+= StaticAnalyzer/Core/Store.cpp
701 SRCS_FUL+= StaticAnalyzer/Core/WorkList.cpp
[all …]
/freebsd-13.1/contrib/llvm-project/clang/include/clang/
H A Dmodule.modulemap121 module Clang_Rewrite { requires cplusplus umbrella "Rewrite/Core" module * { export * } }
136 umbrella "StaticAnalyzer/Core"
138 textual header "StaticAnalyzer/Core/Analyses.def"
139 textual header "StaticAnalyzer/Core/AnalyzerOptions.def"
140 textual header "StaticAnalyzer/Core/PathSensitive/SVals.def"
141 textual header "StaticAnalyzer/Core/PathSensitive/Symbols.def"
142 textual header "StaticAnalyzer/Core/PathSensitive/Regions.def"
176 umbrella "Tooling/Core" module * { export * }
/freebsd-13.1/contrib/llvm-project/clang/include/clang/Basic/
H A DOpenCLOptions.h95 unsigned Core = 0U; member
109 : WithPragma(Pragma), Avail(AvailV), Core(CoreV), Opt(OptV) {} in OpenCLOptionInfo()
111 bool isCore() const { return Core != 0U; } in isCore()
124 return isAvailableIn(LO) && isOpenCLVersionContainedInMask(LO, Core); in isCoreIn()
/freebsd-13.1/contrib/file/magic/Magdir/
H A Ddigital28 # The actual magic number is just "Core", followed by a 2-byte version
29 # number; however, treating any file that begins with "Core" as a Digital
34 0 string Core\001 Alpha COFF format core dump (Digital UNIX)
36 0 string Core\002 Alpha COFF format core dump (Digital UNIX)
/freebsd-13.1/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
15 The DSS Core is the parent of the other DSS modules, and manages clock routing,
27 The DSS Core and the encoders have video port outputs. The structure of the
90 DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
/freebsd-13.1/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-corediv-clock.txt1 * Core Divider Clock bindings for Marvell MVEBU SoCs
12 - reg : must be the register address of Core Divider control register
H A Ddove-divider-clock.txt18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
H A Dmvebu-gated-clock.txt38 15 sata0_core SATA 0 Core
44 21 sata1_core SATA 1 Core
50 29 crypto0_core Cryptographic Unit Port 0 Core
52 31 crypto1_core Cryptographic Unit Port 1 Core
/freebsd-13.1/sys/contrib/device-tree/Bindings/media/
H A Dimg-ir-rev1.txt16 1st: Core clock (defaults to 32.768KHz if omitted).
22 "core": Core clock.
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV67T.td1 //=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=//
60 // Hexagon V67 Tiny Core Resource Definitions -
/freebsd-13.1/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,apr.txt36 3 - DSP Core Service
43 10 - Core voice stream.
44 11 - Core voice processor.
/freebsd-13.1/contrib/llvm-project/lldb/source/Utility/
H A DArchSpec.cpp23 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
34 ArchSpec::Core core;
242 ArchSpec::Core core;
1070 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, in cores_match()
1387 const ArchSpec::Core lhs_core = lhs.GetCore(); in operator <()
1388 const ArchSpec::Core rhs_core = rhs.GetCore(); in operator <()
1446 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || in IsAlwaysThumbInstructions()
1448 GetCore() == ArchSpec::Core::eCore_arm_armv6m || in IsAlwaysThumbInstructions()
1449 GetCore() == ArchSpec::Core::eCore_thumbv7m || in IsAlwaysThumbInstructions()
1450 GetCore() == ArchSpec::Core::eCore_thumbv7em || in IsAlwaysThumbInstructions()
[all …]
/freebsd-13.1/contrib/llvm-project/lldb/include/lldb/Utility/
H A DArchSpec.h101 enum Core { enum
423 Core GetCore() const { return m_core; } in GetCore()
525 Core m_core = kCore_invalid;
/freebsd-13.1/sys/contrib/libsodium/packaging/dotnet-core/
H A DREADME.md1 This directory contains scripts and files to package libsodium for .NET Core.
7 In .NET Core, it is customary to provide pre-compiled binaries for all platforms
26 Version numbers for the packages for .NET Core consist of three components:
/freebsd-13.1/sys/contrib/device-tree/Bindings/timer/
H A Dsifive,clint.yaml7 title: SiFive Core Local Interruptor
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
/freebsd-13.1/sys/contrib/device-tree/Bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/SymbolFile/DWARF/
H A DSymbolFileDWARFProperties.td1 include "../../../../include/lldb/Core/PropertiesBase.td"
/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/JITLoader/GDB/
H A DJITLoaderGDBProperties.td1 include "../../../../include/lldb/Core/PropertiesBase.td"
/freebsd-13.1/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,davinci-rproc.txt7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
18 Each DSP Core sub-system is represented as a single DT node.

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