| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 88 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
125 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
448 case ISD::CopyFromReg: in SUSchedulingCost()
553 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| H A D | StatepointLowering.cpp | 341 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1172 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1174 assert(CopyFromReg.getNode()); in visitGCResult()
1175 setValue(&CI, CopyFromReg); in visitGCResult()
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| H A D | ScheduleDAGRRList.cpp | 323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
711 case ISD::CopyFromReg: in EmitNode()
1279 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2274 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2365 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2436 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2453 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3004 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| H A D | InstrEmitter.cpp | 348 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
1082 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1169 case ISD::CopyFromReg: { in EmitSpecialNode()
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| H A D | ScheduleDAGSDNodes.cpp | 123 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
551 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| H A D | ScheduleDAGFast.cpp | 428 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| H A D | SelectionDAGDumper.cpp | 172 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| H A D | SelectionDAGBuilder.cpp | 5471 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
9212 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
9833 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
10365 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
10374 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 2862 case ISD::CopyFromReg: in SelectCodeCommon()
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| H A D | DAGCombiner.cpp | 1980 case ISD::CopyFromReg: in visitTokenFactor()
8098 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
23169 case ISD::CopyFromReg: in GatherAllAliases()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 247 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
297 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
300 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 208 CopyFromReg, enumerator
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| H A D | SelectionDAG.h | 764 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
774 return getNode(ISD::CopyFromReg, dl, VTs,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 459 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && in isDef32()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 270 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
2203 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2204 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 388 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
394 N->getOpcode() != ISD::CopyFromReg;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1354 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1357 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
1362 N->getOpcode() != ISD::CopyFromReg &&
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| H A D | X86ISelDAGToDAG.cpp | 389 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
2312 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 764 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1646 if (Val.getOpcode() != ISD::CopyFromReg) in IsCopyFromSGPR()
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| H A D | SIISelLowering.cpp | 11956 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
11963 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
11971 case ISD::CopyFromReg: { in isSDNodeSourceOfDivergence()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3638 if (Ptr.getOpcode() == ISD::CopyFromReg && in Select()
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| H A D | ARMISelLowering.cpp | 2856 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
14391 Copy->getOpcode() == ISD::CopyFromReg) { in PerformVMOVhrCombine()
14394 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), N->getValueType(0), Ops); in PerformVMOVhrCombine()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4483 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
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