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Searched refs:CheckAll (Results 1 – 12 of 12) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedPredicates.td23 def ZeroIdiomVPERMPredicate : CheckAll<[
30 def IsThreeOperandsLEAPredicate: CheckAll<[
41 CheckAll<[
125 def IsAtomicCompareAndSwap_8 : CheckAll<[
130 def IsAtomicCompareAndSwap : CheckAll<[
135 def IsAtomicCompareAndSwap8B : CheckAll<[
140 def IsAtomicCompareAndSwap16B : CheckAll<[
H A DX86ScheduleBtVer2.td943 CheckAll<[
H A DX86ScheduleBdVer2.td564 CheckAll<[
H A DX86SchedHaswell.td1939 CheckAll<[
H A DX86ScheduleZnver3.td592 CheckAll<[
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td18 CheckAll<
29 CheckAll<[CheckOpcode<[BLR]>,
40 CheckAll<
85 CheckAll<
132 CheckAll<
145 CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
H A DAArch64SchedPredicates.td64 def CheckHForm : CheckAll<[CheckIsRegOperand<0>,
99 def CheckSForm : CheckAll<[CheckIsRegOperand<0>,
134 def CheckDForm : CheckAll<[CheckIsRegOperand<0>,
169 def CheckQForm : CheckAll<[CheckIsRegOperand<0>,
352 CheckAll<
366 CheckAll<
421 CheckAll<
434 CheckAll<
/freebsd-13.1/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsatimer.c143 saRoot->CheckAll++; in saTimerTick()
150 saRoot->CheckAll, in saTimerTick()
156 saRoot->CheckAll, in saTimerTick()
167 saRoot->CheckAll, in saTimerTick()
175 if( saRoot->CheckAll > 1) in saTimerTick()
197 if(saRoot->CheckAll ) in saTimerTick()
H A Dsatypes.h336 bit32 CheckAll; member
H A Dsaint.c873 else if (saRoot->CheckAll) in saDelayedInterruptHandler()
896 else if (saRoot->CheckAll) in saDelayedInterruptHandler()
906 saRoot->CheckAll = 0; in saDelayedInterruptHandler()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td16 // def MCInstPredicateExample : CheckAll<[
24 // The `CheckAll` from the example defines a composition of three different
186 // A sequence of predicates. It is used as the base class for CheckAll, and
193 class CheckAll<list<MCInstPredicate> Sequence>
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td24 def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;
36 class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[
48 CheckAll<[