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Searched refs:CSR_READ_1 (Results 1 – 25 of 30) sorted by relevance

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/freebsd-13.1/sys/dev/ste/
H A Dif_ste.c215 val = CSR_READ_1(sc, STE_PHYCTL); in ste_mii_bitbang_read()
433 rxcfg = CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
457 CSR_READ_1(sc, STE_RX_MODE); in ste_rxfilter()
818 CSR_READ_1(sc, STE_STAT_RX_BCAST); in ste_stats_clear()
819 CSR_READ_1(sc, STE_STAT_RX_MCAST); in ste_stats_clear()
820 CSR_READ_1(sc, STE_STAT_RX_LOST); in ste_stats_clear()
825 CSR_READ_1(sc, STE_STAT_TX_BCAST); in ste_stats_clear()
826 CSR_READ_1(sc, STE_STAT_TX_MCAST); in ste_stats_clear()
831 CSR_READ_1(sc, STE_STAT_TX_DEFER); in ste_stats_clear()
833 CSR_READ_1(sc, STE_STAT_TX_ABORT); in ste_stats_clear()
[all …]
H A Dif_stereg.h494 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13.1/sys/dev/re/
H A Dif_re.c360 CSR_READ_1(sc, RL_EECMD) | x)
364 CSR_READ_1(sc, RL_EECMD) & ~x)
1325 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1362 cfg = CSR_READ_1(sc, RL_CFG2); in re_attach()
1559 cfg = CSR_READ_1(sc, sc->rl_cfg1); in re_attach()
1562 cfg = CSR_READ_1(sc, sc->rl_cfg5); in re_attach()
3901 v = CSR_READ_1(sc, sc->rl_cfg1); in re_setwol()
3907 v = CSR_READ_1(sc, sc->rl_cfg3); in re_setwol()
3913 v = CSR_READ_1(sc, sc->rl_cfg5); in re_setwol()
3958 v = CSR_READ_1(sc, sc->rl_cfg3); in re_clrwol()
[all …]
/freebsd-13.1/sys/dev/vge/
H A Dif_vge.c262 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword()
303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom()
524 cfg = CSR_READ_1(sc, VGE_RXCFG); in vge_setvlan()
577 rxcfg = CSR_READ_1(sc, VGE_RXCTL); in vge_rxfilter()
1090 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & in vge_attach()
1674 physts = CSR_READ_1(sc, VGE_PHYSTS0); in vge_link_statchg()
2763 intctl = CSR_READ_1(sc, VGE_INTCTL1); in vge_intr_holdoff()
2896 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_setwol()
2900 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_setwol()
2918 val = CSR_READ_1(sc, VGE_PWRSTAT); in vge_clrwol()
[all …]
H A Dif_vgevar.h230 #define CSR_READ_1(sc, reg) \ macro
234 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
241 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-13.1/sys/dev/vr/
H A Dif_vr.c326 cr0 = CSR_READ_1(sc, VR_CR0); in vr_miibus_statchg()
327 cr1 = CSR_READ_1(sc, VR_CR1); in vr_miibus_statchg()
351 fc = CSR_READ_1(sc, VR_FLOWCR1); in vr_miibus_statchg()
2358 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_start()
2377 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_start()
2393 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_stop()
2399 cmd = CSR_READ_1(sc, VR_CR0); in vr_tx_stop()
2415 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_stop()
2421 cmd = CSR_READ_1(sc, VR_CR0); in vr_rx_stop()
2582 v = CSR_READ_1(sc, VR_STICKHW); in vr_setwol()
[all …]
H A Dif_vrreg.h756 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-13.1/sys/dev/rl/
H A Dif_rl.c269 CSR_READ_1(sc, RL_EECMD) | x)
273 CSR_READ_1(sc, RL_EECMD) & ~x)
369 val = CSR_READ_1(sc, RL_MII); in rl_mii_bitbang_read()
426 return (CSR_READ_1(sc, RL_MEDIASTAT)); in rl_miibus_readreg()
780 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in rl_attach()
1931 if ((CSR_READ_1(sc, RL_COMMAND) & in rl_stop()
2068 v = CSR_READ_1(sc, sc->rl_cfg1); in rl_setwol()
2074 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_setwol()
2080 v = CSR_READ_1(sc, sc->rl_cfg5); in rl_setwol()
2115 v = CSR_READ_1(sc, sc->rl_cfg3); in rl_clrwol()
[all …]
H A Dif_rlreg.h959 #define CSR_READ_1(sc, reg) \ macro
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd-13.1/sys/dev/ipw/
H A Dif_ipwreg.h327 #define CSR_READ_1(sc, reg) \ macro
354 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
/freebsd-13.1/sys/dev/fxp/
H A Dif_fxp.c339 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) in fxp_scb_wait()
342 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH); in fxp_scb_wait()
343 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS); in fxp_scb_wait()
345 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), in fxp_scb_wait()
346 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), in fxp_scb_wait()
347 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w); in fxp_scb_wait()
920 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_attach()
1118 CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_resume()
1695 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); in fxp_poll()
2162 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { in fxp_tick()
[all …]
H A Dif_fxpvar.h246 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
/freebsd-13.1/sys/dev/xl/
H A Dif_xl.c458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_miibus_statchg()
630 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90x()
690 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_rxfilter_90xB()
819 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode()
2092 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc()
2315 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update()
2331 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update()
2830 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init_locked()
2956 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
2965 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
H A Dif_xlreg.h665 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13.1/sys/dev/msk/
H A Dif_msk.c1211 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; in mskc_setup_rambuffer()
1673 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); in msk_attach()
1787 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); in mskc_attach()
1788 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; in mskc_attach()
1826 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); in mskc_attach()
1829 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in mskc_attach()
3846 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); in msk_init_locked()
4101 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
4116 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); in msk_set_rambuffer()
4239 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == in msk_stop()
[all …]
H A Dif_mskreg.h2136 #define CSR_READ_1(sc, reg) \ macro
2158 CSR_READ_1((sc_if)->msk_softc, (reg))
/freebsd-13.1/sys/dev/stge/
H A Dif_stge.c259 val = CSR_READ_1(sc, STGE_PhyCtrl); in stge_mii_bitbang_read()
298 error = CSR_READ_1(sc, STGE_PhyCtrl); in stge_miibus_readreg()
596 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
992 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_setwol()
1038 v = CSR_READ_1(sc, STGE_WakeEvent); in stge_resume()
1960 v = CSR_READ_1(sc, STGE_PhySet); in stge_reset()
H A Dif_stgereg.h101 #define CSR_READ_1(_sc, reg) \ macro
/freebsd-13.1/sys/dev/my/
H A Dif_myreg.h401 #define CSR_READ_1(sc, reg) \ macro
H A Dif_my.c858 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); in my_attach()
/freebsd-13.1/sys/dev/lge/
H A Dif_lge.c673 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
1003 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1209 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
H A Dif_lgereg.h549 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13.1/sys/dev/an/
H A Dif_anreg.h56 #define CSR_READ_1(sc, reg) bus_read_1(sc->port_res, reg) macro
/freebsd-13.1/sys/dev/iwi/
H A Dif_iwireg.h573 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13.1/sys/dev/sk/
H A Dif_skreg.h1287 #define CSR_READ_1(sc, reg) \ macro

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