Searched refs:CSNEG (Results 1 – 13 of 13) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 320 CSNEG, // Conditional select negate. enumerator
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| H A D | ARMISelLowering.cpp | 1823 MAKE_CASE(ARMISD::CSNEG) in getTargetNodeName() 5351 Opcode = ARMISD::CSNEG; in LowerSELECT_CC() 18898 case ARMISD::CSNEG: { in computeKnownBitsForTargetNode() 18911 else if (Op.getOpcode() == ARMISD::CSNEG) in computeKnownBitsForTargetNode()
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| H A D | ARMInstrInfo.td | 119 def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 70 CSNEG, // Conditional select negate. enumerator
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| H A D | AArch64SchedThunderX2T99.td | 434 "CSNEG(W|X)r")>; 456 "CSNEG(W|X)r")>; 475 "CSNEG(W|X)r")>;
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| H A D | AArch64SchedThunderX3T110.td | 693 "CSNEG(W|X)r")>; 715 "CSNEG(W|X)r")>; 734 "CSNEG(W|X)r")>;
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| H A D | AArch64SchedTSV110.td | 376 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedCyclone.td | 148 // CSEL,CSINC,CSINV,CSNEG
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| H A D | AArch64SchedA64FX.td | 828 "CSNEG(W|X)r")>; 849 "CSNEG(W|X)r")>; 867 "CSNEG(W|X)r")>;
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| H A D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedKryoDetails.td | 549 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| H A D | AArch64ISelLowering.cpp | 1903 MAKE_CASE(AArch64ISD::CSNEG) in getTargetNodeName() 7367 Opcode = AArch64ISD::CSNEG; in LowerSELECT_CC() 7422 } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) { in LowerSELECT_CC()
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| H A D | AArch64InstrInfo.td | 445 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>; 2135 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
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