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Searched refs:CSINV (Results 1 – 13 of 13) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h319 CSINV, // Conditional select invert. enumerator
H A DARMISelLowering.cpp1822 MAKE_CASE(ARMISD::CSINV) in getTargetNodeName()
5349 Opcode = ARMISD::CSINV; in LowerSELECT_CC()
13345 return DAG.getNode(ARMISD::CSINV, SDLoc(N), MVT::i32, in PerformSubCSINCCombine()
18897 case ARMISD::CSINV: in computeKnownBitsForTargetNode()
18909 else if (Op.getOpcode() == ARMISD::CSINV) in computeKnownBitsForTargetNode()
H A DARMInstrInfo.td118 def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h69 CSINV, // Conditional select invert. enumerator
H A DAArch64SchedThunderX2T99.td433 "CSINC(W|X)r", "CSINV(W|X)r",
455 "CSINC(W|X)r", "CSINV(W|X)r",
474 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64SchedThunderX3T110.td692 "CSINC(W|X)r", "CSINV(W|X)r",
714 "CSINC(W|X)r", "CSINV(W|X)r",
733 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64SchedTSV110.td376 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedCyclone.td148 // CSEL,CSINC,CSINV,CSNEG
H A DAArch64SchedA64FX.td827 "CSINC(W|X)r", "CSINV(W|X)r",
848 "CSINC(W|X)r", "CSINV(W|X)r",
866 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64SchedFalkorDetails.td894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedKryoDetails.td555 (instregex "(CSINV)(W|X)r")>;
H A DAArch64ISelLowering.cpp1902 MAKE_CASE(AArch64ISD::CSINV) in getTargetNodeName()
7364 Opcode = AArch64ISD::CSINV; in LowerSELECT_CC()
7428 Opcode = AArch64ISD::CSINV; in LowerSELECT_CC()
H A DAArch64InstrInfo.td444 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
2134 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;