Searched refs:CSINC (Results 1 – 13 of 13) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 321 CSINC, // Conditional select increment. enumerator
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| H A D | ARMISelLowering.cpp | 1824 MAKE_CASE(ARMISD::CSINC) in getTargetNodeName() 5353 Opcode = ARMISD::CSINC; in LowerSELECT_CC() 5355 Opcode = ARMISD::CSINC; in LowerSELECT_CC() 5364 if (Opcode != ARMISD::CSINC && in LowerSELECT_CC() 5374 if (FVal == 0 && Opcode != ARMISD::CSINC) { in LowerSELECT_CC() 13337 SDValue CSINC = N->getOperand(1); in PerformSubCSINCCombine() local 13338 if (CSINC.getOpcode() != ARMISD::CSINC || !CSINC.hasOneUse()) in PerformSubCSINCCombine() 13348 CSINC.getOperand(1), CSINC.getOperand(2), in PerformSubCSINCCombine() 13349 CSINC.getOperand(3)); in PerformSubCSINCCombine() 18896 case ARMISD::CSINC: in computeKnownBitsForTargetNode() [all …]
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| H A D | ARMInstrInfo.td | 120 def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 71 CSINC, // Conditional select increment. enumerator
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| H A D | AArch64SchedThunderX2T99.td | 433 "CSINC(W|X)r", "CSINV(W|X)r", 455 "CSINC(W|X)r", "CSINV(W|X)r", 474 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64SchedThunderX3T110.td | 692 "CSINC(W|X)r", "CSINV(W|X)r", 714 "CSINC(W|X)r", "CSINV(W|X)r", 733 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64SchedTSV110.td | 376 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedCyclone.td | 148 // CSEL,CSINC,CSINV,CSNEG
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| H A D | AArch64SchedA64FX.td | 827 "CSINC(W|X)r", "CSINV(W|X)r", 848 "CSINC(W|X)r", "CSINV(W|X)r", 866 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedKryoDetails.td | 549 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| H A D | AArch64ISelLowering.cpp | 1904 MAKE_CASE(AArch64ISD::CSINC) in getTargetNodeName() 7378 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC() 7386 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC() 16926 AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32), in PerformDAGCombine()
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| H A D | AArch64InstrInfo.td | 446 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>; 2133 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
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